Semiconductor device with a conductive layer including a copper layer with a dopant
    22.
    发明授权
    Semiconductor device with a conductive layer including a copper layer with a dopant 有权
    具有包括具有掺杂剂的铜层的导电层的半导体器件

    公开(公告)号:US07187080B2

    公开(公告)日:2007-03-06

    申请号:US10964963

    申请日:2004-10-14

    IPC分类号: H01L23/48

    摘要: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

    摘要翻译: 一种制造半导体器件的方法包括以下步骤:提供半导体衬底(202),在半导体衬底(202)上形成电介质层(204),并蚀刻电介质层(204)中的沟槽或通孔(206) )以暴露半导体衬底(202)的表面的一部分。 该方法还包括在沟槽或通孔(206)内形成导电层(212,220)的步骤。 该方法还包括以下步骤:抛光导电层(220)的一部分并在预定温度下退火导电层(212,220)。 此外,导电层(212,220)还包括掺杂剂,并且掺杂剂基本上扩散到导电层(212,220)的顶侧的表面,以形成掺杂剂氧化物层(212a,220a),当 导电层(212,220)在预定温度下退火,掺杂剂暴露于氧气。

    Methods for forming multiple damascene layers
    27.
    发明授权
    Methods for forming multiple damascene layers 有权
    形成多个镶嵌层的方法

    公开(公告)号:US06723636B1

    公开(公告)日:2004-04-20

    申请号:US10447513

    申请日:2003-05-28

    IPC分类号: H01L214763

    摘要: According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via through a dielectric layer that overlies a first layer. The first layer comprises a conductive portion that at least partly underlies the via. The method also includes overfilling the via with a dielectric material to form a second layer that overlies the dielectric layer. The method also includes forming a trench that is connected to the via by etching through the second layer and the dielectric material in the via.

    摘要翻译: 根据本发明的一个实施例,提供了一种用于形成半导体器件的多层的方法。 该方法包括通过覆盖在第一层上的电介质层限定通孔。 第一层包括至少部分地位于通孔下方的导电部分。 该方法还包括用电介质材料过填充通孔以形成覆盖在电介质层上的第二层。 该方法还包括通过蚀刻穿过第二层和通孔中的介电材料形成连接到通孔的沟槽。