公开(公告)号：US08772951B1

公开(公告)日：2014-07-08

申请号：US14014192

申请日：2013-08-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Omar James Bchir

IPC: H01L21/4763 ,  H01L29/40

CPC classification number: H01L23/498 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09227

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect embedded in a first surface of the first dielectric layer, and a second interconnect on the first surface of the first dielectric layer. The first interconnect is offset from the first surface of the first dielectric layer. The first interconnect being offset towards an inner portion of the first dielectric layer. In some implementations, the substrate further includes a third interconnect embedded in the first surface of the first dielectric layer, and a fourth interconnect on the first surface of the first dielectric layer. The first interconnect and the second interconnect are adjacent interconnects. In some implementations, the substrate further includes a first pad on the first surface of the first dielectric layer. The first pad is coupled to the first interconnect.

Abstract translation: 一些新颖的特征涉及包括第一介电层，嵌入在第一介电层的第一表面中的第一互连以及在第一介电层的第一表面上的第二互连的衬底。 第一互连件与第一介电层的第一表面偏移。 第一互连件朝向第一介电层的内部部分偏移。 在一些实施方案中，衬底还包括嵌入在第一介电层的第一表面中的第三互连和在第一介电层的第一表面上的第四互连。 第一互连和第二互连是相邻的互连。 在一些实施方案中，衬底还包括在第一介电层的第一表面上的第一焊盘。 第一焊盘耦合到第一互连。

公开(公告)号：US20140159238A1

公开(公告)日：2014-06-12

申请号：US13708221

申请日：2012-12-07

Applicant: QUALCOMM INCORPORATED

Inventor： Manuel Aldrete ,  Milind P. Shah ,  Omar J. Bchir ,  Houssam W. Jomaa ,  Chin-Kwan Kim

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L23/488 ,  H01L21/50 ,  H01L23/49838 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces. The first set of traces has a first pitch. The second set of traces has a second pitch. The first pitch is less than the second pitch. In some implementations, a pitch of a set of traces defines a center to center distance between two neighboring traces, or bonding pads on a substrate. The first die is coupled to the substrate by a thermal compression bonding process. In some implementations, the first die is coupled to the first set of traces of the substrate. The second die is coupled to the substrate by a reflow bonding process. In some implementations, the second die is coupled to the second set of traces of the substrate.

Abstract translation: 本公开的一些示例性实施方式涉及包括基板，第一管芯和第二管芯的集成电路封装。 衬底包括第一组迹线和第二组迹线。 第一组轨迹具有第一音调。 第二组轨迹具有第二个间距。 第一节距小于第二节距。 在一些实施方案中，一组迹线的间距限定了两个相邻迹线之间的中心到中心距离，或者衬底上的接合焊盘。 第一管芯通过热压接工艺耦合到衬底。 在一些实施方式中，第一管芯耦合到衬底的第一组迹线。 第二管芯通过回流焊接工艺耦合到衬底。 在一些实施方式中，第二管芯耦合到衬底的第二组迹线。

公开(公告)号：US20140131857A1

公开(公告)日：2014-05-15

申请号：US13771524

申请日：2013-02-20

Applicant: QUALCOMM INCORPORATED

Inventor： Omar J. Bchir ,  Milind P. Shah ,  Houssam W. Jomaa ,  Manuel Aldrete ,  Chin-Kwan Kim

IPC: H01L23/498

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/10175 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83192 ,  H05K1/092 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.

公开(公告)号：US12160952B2

公开(公告)日：2024-12-03

申请号：US17934651

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Biancun Xie ,  Shree Krishna Pandey ,  Chin-Kwan Kim ,  Ryan Lane ,  Charles David Paynter

IPC: H05K1/00 ,  H05K1/02 ,  H05K3/46

Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

公开(公告)号：US11776888B2

公开(公告)日：2023-10-03

申请号：US17334610

申请日：2021-05-28

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Hong Bok We ,  Chin-Kwan Kim ,  Milind Shah

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

公开(公告)号：US20220068780A1

公开(公告)日：2022-03-03

申请号：US17405494

申请日：2021-08-18

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Chin-Kwan Kim ,  Joonsuk Park

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (μm)/5.0 μm or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.

公开(公告)号：US11075260B2

公开(公告)日：2021-07-27

申请号：US16176915

申请日：2018-10-31

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Chin-Kwan Kim ,  Hong Bok We ,  Jaehyun Yeon

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31

Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.

公开(公告)号：US11043740B2

公开(公告)日：2021-06-22

申请号：US16411883

申请日：2019-05-14

Applicant: QUALCOMM Incorporated

Inventor： Suhyung Hwang ,  Chin-Kwan Kim ,  Hong Bok We ,  Jaehyun Yeon

IPC: H01Q1/52

Abstract: Methods and apparatuses for enhancing antenna modules with a shield layer. The apparatus includes an antenna module having an antenna layer. The antenna layer includes an antenna. The antenna module further includes a signal routing layer; a radio frequency (RF) communication component disposed on the signal routing layer; a shield cover encasing the RF communication component; and a shield layer. The antenna module further includes an antenna module side. The antenna module side includes a side of the signal routing layer and a side of the antenna layer. The shield layer covers a portion of the antenna module side such that at least a portion of the side of the antenna layer is uncovered.

公开(公告)号：US10734332B2

公开(公告)日：2020-08-04

申请号：US15839831

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jon Bradley Lasiter ,  Ravindra Vaman Shenoy ,  Donald William Kidwell, Jr. ,  Mohammad Ali Tassoudji ,  Vladimir Aparin ,  Seong Heon Jeong ,  Jeremy Dunworth ,  Alireza Mohammadian ,  Mario Francisco Velez ,  Chin-Kwan Kim

IPC: H01L23/00 ,  H01L23/66 ,  H01L23/498 ,  H01L23/552 ,  H01L23/31 ,  H01L21/50 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q21/10 ,  H01Q19/24 ,  H01Q9/16 ,  H01L23/10

Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.

公开(公告)号：US10510733B2

公开(公告)日：2019-12-17

申请号：US16185635

申请日：2018-11-09

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Chin-Kwan Kim ,  Milind Shah

IPC: H01L25/10 ,  H01L23/552 ,  H01L23/66 ,  H01L25/065 ,  H04W4/80 ,  H01L25/00 ,  H04W4/00 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56

Abstract: A device that includes a printed circuit board (PCB), a package on package (PoP) device, a first encapsulation layer, and a second encapsulation layer. The package on package (PoP) device is coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package having a first electronic package component, a second package coupled to the first package, a gap controller configured to provide a spacing between the first electronic package component and the second package. The gap controller includes a spacer and an adhesive layer. The first encapsulation layer is formed between the first package and the second package. The first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer. The second encapsulation layer is configured to at least partially encapsulates the package on package (PoP) device. The device is configured to provide cellular functionality.