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    SYSTEMS AND METHODS TO REDUCE PARASITIC CAPACITANCE
    24.
    发明申请
    SYSTEMS AND METHODS TO REDUCE PARASITIC CAPACITANCE 有权
    降低PARASITIC电容的系统和方法

    公开(公告)号：US20160293475A1

    公开(公告)日：2016-10-06

    申请号：US14676728

    申请日：2015-04-01

    Applicant: QUALCOMM Incorporated

    Inventor： Shiqun Gu ,  Vidhya Ramachandran ,  Christine Sung-An Hau-Riege ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Jihong Choi ,  Jun Chen ,  Choh Fei Yeap

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

    Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

    Abstract translation: 公开了减小寄生电容的装置和方法。 器件可以包括电介质层。 该器件可以包括第一和第二导电结构以及靠近电介质层的蚀刻停止层。 蚀刻停止层可以限定靠近第一和第二导电结构之间的电介质层的区域的第一和第二开口。 该装置可以包括区域内的第一和第二气隙。 该装置可以包括靠近蚀刻停止层（例如，在上方，上方或上方）的材料层。 靠近蚀刻停止层的材料层可以覆盖第一和第二气隙。

    STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINES ON SEPARATE METAL LAYERS FOR INCREASED PERFORMANCE, AND RELATED METHODS
    27.
    发明申请
    STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINES ON SEPARATE METAL LAYERS FOR INCREASED PERFORMANCE, AND RELATED METHODS 有权
    静态随机访问存储器（SRAM）位元件，具有用于增加性能的单独金属层上的边界和相关方法

    公开(公告)号：US20160163713A1

    公开(公告)日：2016-06-09

    申请号：US14559205

    申请日：2014-12-03

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

    IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L23/528 ,  H01L21/768

    CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.

    Abstract translation: 公开了在单独的金属层上具有字线的静态随机存取存储器（SRAM）位单元，以提高性能。 在一个方面，公开了采用第二金属层中的写入字线，第三金属层中的第一读取字线和第四金属层中的第二读取字线的SRAM位单元。 在单独的金属层中使用字线允许字线增加宽度，这降低了字线电阻，减少了访问时间，并提高了SRAM位单元的性能。 为了在单独的金属层中采用字线，采用第一金属层中的多个轨迹。 为了将读取的字线耦合到轨道以与SRAM位单元晶体管通信，着陆焊盘设置在设置在第一金属层中的相应的轨道上。 对应于写入字线的着陆垫被放置在设置在第一金属层中的对应的轨道上。

    SHARED GLOBAL READ AND WRITE WORD LINES
    29.
    发明申请
    SHARED GLOBAL READ AND WRITE WORD LINES 有权
    共享全球阅读和写字线

    公开(公告)号：US20160141021A1

    公开(公告)日：2016-05-19

    申请号：US14546980

    申请日：2014-11-18

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Ping Liu ,  Kern Rim ,  Choh Fei Yeap

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0688 ,  H01L27/1104

    Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

    Abstract translation: 一种装置包括包括第一行位单元和第二行位单元的位单元阵列。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第一全局读取字线。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第二全局读取字线。 该装置还包括全局写入字线，其被配置为选择性地耦合到第一行位单元和第二行位单元。 第一个全局读取字线，第二个全局读取字线和全局写入字线位于公共金属层中。

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