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公开(公告)号：US09608586B2
公开(公告)日：2017-03-28
申请号：US14639553
申请日：2015-03-05
Applicant: QUALCOMM Incorporated
Inventor： Li Du , Sang Min Lee , Dongwon Seo
CPC classification number: H03G3/3042 , G05F1/561 , H03F1/0233 , H03F3/193 , H03F3/21 , H03F2200/21 , H03F2200/252 , H03F2200/451 , H03K5/24
Abstract: A converter including: an amplifier having first and second input terminals and an output terminal, the first input terminal configured to receive a reference voltage; an array of resistors configured to generate a tuning voltage; and a first plurality of switches coupled to the second input terminal of the amplifier and the array of resistors, the first plurality of switches configured to adjust a gain of the amplifier by selecting at least one resistor in the array of resistors to connect to the second input terminal of the amplifier.
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22.发明授权公开(公告)号：US09553573B2
公开(公告)日：2017-01-24
申请号：US14487654
申请日：2014-09-16
Applicant: QUALCOMM Incorporated
Inventor： Derui Kong , Sang Min Lee , Michael Joseph McGowan , Dongwon Seo
CPC classification number: H03K17/16 , H03F1/14 , H03F3/45188
Abstract: A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.
Abstract translation: 提供了一种方法和装置。 该装置可以是用于调整电路的净电容的电容元件。 该装置可以被配置为耦合到该电路。 该装置可以被配置为调整电路的净电容以去耦合电路的共模和差分环路带宽调整。 电容元件可以包括配置为耦合到电路的差分节点的一对交叉耦合电容器，以及耦合到相应电容器的一对负增益缓冲器。
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公开(公告)号：US09178524B1
公开(公告)日：2015-11-03
申请号：US14493254
申请日：2014-09-22
Applicant: QUALCOMM Incorporated
Inventor： Sang Min Lee , Dongwon Seo
CPC classification number: H03M1/0863 , H03M1/0612 , H03M1/0881 , H03M1/687 , H03M1/785
Abstract: The apparatus may be an N-bit DAC including (2M−1) parallel stages associated with M most significant bits, and (N-M) stages associated with (N-M) least significant bits. The (2M−1) parallel stages may deliver a first current to current-summing nodes of the DAC. The (N-M) stages may include a resistive network and a second pair of switches, and may deliver a second current to the resistive network of the stage. Each resistive network may scale the respectively delivered currents according to a binary weight of a stage corresponding to the resistive network, and may deliver the scaled currents to the pair of current-summing nodes. At least one of the (N-M) stages may be separated from the remaining stages.
Abstract translation: 该装置可以是包括与M个最高有效位相关联的（2M-1）个并行级和与（N-M）个最低有效位相关联的（N-M）级的N位DAC。 （2M-1）并联级可以将第一电流传送到DAC的电流求和节点。 （N-M）级可以包括电阻网络和第二对开关，并且可以将第二电流传递到级的电阻网络。 每个电阻网络可以根据对应于电阻网络的级的二进制权重来缩放分别传递的电流，并且可以将缩放的电流传送到一对电流求和节点。 （N-M）级中的至少一个可以与其余级分离。
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24.发明授权Techniques to reduce harmonic distortions of impedance attenuators for low-power wideband high-resolution DACs 有权降低低功耗宽带高分辨率DAC阻抗衰减器谐波失真的技术公开(公告)号：US08872685B2
公开(公告)日：2014-10-28
申请号：US13839763
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Tongyu Song , Sang Min Lee , Derui Kong , Dongwon Seo
CPC classification number: H03M1/74 , H03F3/19 , H03F3/211 , H03F3/245 , H03F3/45192 , H03F3/4565 , H03F3/72 , H03F2203/45466 , H03F2203/45512 , H03F2203/45562 , H03F2203/45631 , H03F2203/45634 , H03F2203/45644 , H03F2203/45686 , H03F2203/45701 , H03F2203/45702 , H03F2203/7236 , H03M1/0614
Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.
Abstract translation: 数模转换器（DAC）部分地包括响应于数字信号向一对当前求和节点提供电流的多个输入级，以及耦合在当前求和节点和输出端之间的阻抗衰减器 的DAC。 除了其他功能之外，阻抗衰减器还适用于增加输出负载的阻抗范围，以解决由于工艺，电压和温度的变化而导致的输出负载阻抗的变化，并且将由总和看到的阻抗解耦 节点从负载阻抗。 阻抗衰减器还包括具有可编程共模增益带宽的差分输入差分输出放大器，以控制放大器的谐波失真。 阻抗衰减器可选地包括一对交叉耦合电容器，以控制放大器的谐波失真。
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公开(公告)号：US11539371B1
公开(公告)日：2022-12-27
申请号：US17449056
申请日：2021-09-27
Applicant: QUALCOMM Incorporated
Inventor： Zhilong Tang , Dongwon Seo
IPC: H03M1/10
Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current sources, a plurality of calibration DACs, each coupled to a respective one of the plurality of current sources, a reference current source, and a current mirror having a first branch selectively coupled to the plurality of current sources, wherein a second branch of the current mirror is coupled to the reference current source. The DAC system also includes a first error DAC selectively coupled to the first branch and the second branch of the current mirror, and a second error DAC selectively coupled to the first branch and the second branch of the current mirror.
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Patent Agency Ranking
公开(公告)号：US10516412B1
公开(公告)日：2019-12-24
申请号：US16138499
申请日：2018-09-21
Applicant: QUALCOMM INCORPORATED
Inventor： Shahin Mehdizad Taleie , Ashok Swaminathan , Sudharsan Kanagaraj , Negar Rashidi , Siyu Yang , Behnam Sedighi , Honghao Ji , Jaswinder Singh , Andrew Weil , Dongwon Seo , Xilin Liu
Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.
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公开(公告)号：US10461768B1
公开(公告)日：2019-10-29
申请号：US16208724
申请日：2018-12-04
Applicant: QUALCOMM Incorporated
Inventor： Zongyu Dong , Andrew Weil , Dongwon Seo
Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of transistors selectively coupled to an output of the DAC, and a biasing circuit coupled to gates of the plurality of transistors. The biasing circuit may include a first transistor having a gate coupled to a drain of the first transistor, a first buffer having an input coupled to the gate of the first transistor, a second transistor having a gate coupled to an output of the first buffer, a first resistive-capacitive (RC) circuit having a first resistive element and a first capacitive element, the first RC circuit being coupled between the gate of the first transistor and the gate of the second transistor, and a first switch coupled between the first resistive element and the first capacitive element.
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公开(公告)号：US10305361B2
公开(公告)日：2019-05-28
申请号：US15710704
申请日：2017-09-20
Applicant: QUALCOMM Incorporated
Inventor： Nitz Saputra , Sang Min Lee , Dongwon Seo , Vinay Kundur , Behnam Sedighi , Honghao Ji
Abstract: A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.
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29.发明申请公开(公告)号：US20170257066A1
公开(公告)日：2017-09-07
申请号：US15188552
申请日：2016-06-21
Applicant: QUALCOMM Incorporated
Inventor： NITZ SAPUTRA , Sang Min Lee , Dongwon Seo
Abstract: Circuits and methods for compensating variation in an amplitude-regulated oscillator are provided. In one example, the oscillator includes a diode clamp having back-to-back diode-connected transistors with body terminals. Circuits and methods modulate a body-source voltage of the diode-connected transistors to compensate for process, temperature, and voltage variation.
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公开(公告)号：US20160248432A1
公开(公告)日：2016-08-25
申请号：US14631578
申请日：2015-02-25
Applicant: QUALCOMM, Incorporated
Inventor： Mohammadhossein Naderi Alizadeh , Shahin Mehdizad Taleie , Dongwon Seo
CPC classification number: H03M1/0626 , H03M1/002 , H03M1/687 , H03M3/368 , H03M3/502 , H03M7/3042
Abstract: In one embodiment, a method for converting an input digital signal into an analog signal is provided. The method comprises modulating the input digital signal into a modulated digital signal, and converting the modulated digital signal into the analog signal using a digital-to-analog converter (DAC). The modulation shapes quantization noise of the DAC to place a notch at a frequency within an out-of-bound frequency band to reduce the quantization noise within the out-of-bound frequency band.
Abstract translation: 在一个实施例中，提供了一种将输入数字信号转换为模拟信号的方法。 该方法包括将输入数字信号调制成调制数字信号，并使用数模转换器（DAC）将调制的数字信号转换为模拟信号。 调制形成DAC的量化噪声，以将陷波放置在超出频带内的频率上，以减小超出频带内的量化噪声。
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