公开(公告)号：US20160124030A1

公开(公告)日：2016-05-05

申请号：US14533950

申请日：2014-11-05

Applicant: QUALCOMM Incorporated

Inventor： Chuang Zhang ,  Zhengming Fu ,  Nan Chen

IPC: G01R19/25 ,  G01R19/32

CPC classification number: G01R19/25 ,  G01R19/0092 ,  G01R19/32

Abstract: In one embodiment, a method for measuring current is described herein. The method comprises shorting first and second inputs of an amplifying circuit to generate a first output signal, and converting the first output signal into an offset cancelation value. The method also comprises passing a current through a power switch, wherein the current generates a voltage drop across the power switch, applying the voltage drop across the first and second inputs of the amplifying circuit to generate a second output signal, and converting the second output signal into a current value. The method further comprises subtracting the offset cancelation value from the current value to generate an offset-compensated current value.

Abstract translation: 在一个实施例中，这里描述了一种用于测量电流的方法。 该方法包括缩短放大电路的第一和第二输入以产生第一输出信号，并将第一输出信号转换成偏移消除值。 该方法还包括使电流通过电源开关，其中电流在功率开关两端产生电压降，在放大电路的第一和第二输入端施加电压降，以产生第二输出信号，并转换第二输出 信号变成当前值。 该方法还包括从当前值减去偏移消除值以产生偏移补偿电流值。

公开(公告)号：US20140266343A1

公开(公告)日：2014-09-18

申请号：US13831639

申请日：2013-03-15

Applicant: Qualcomm Incorporated

Inventor： Yu Song ,  Nan Chen

IPC: H03L7/08

CPC classification number: H03L7/0802 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/093

Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.

Abstract translation: 本文描述了用于降低锁相环（PLL）的环路滤波器中的噪声和功耗的技术。 在一个实施例中，用于PLL的环路滤波器包括第一比例电容器，第二比例电容器，有源器件和多个开关。 多个开关被配置为将第一比例电容器和第二比例电容器交替地耦合到第一电荷泵，以将来自有源器件的噪声交替耦合到第一比例电容器和第二比例电容器，并且交替地耦合第一比例电容器 电容器和第二比例电容器组成反馈电路，其中反馈电路产生环路滤波器的输出电压。

公开(公告)号：US11145608B2

公开(公告)日：2021-10-12

申请号：US16359319

申请日：2019-03-20

Applicant: QUALCOMM Incorporated

Inventor： Alan Lewis ,  Zhengming Fu ,  Nan Chen ,  Adam Polak ,  Laura Fuentes ,  Gregory Bullard ,  Mark Todorovich

IPC: H01L23/00 ,  H01L27/144 ,  G06F21/75

Abstract: Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

公开(公告)号：US09858217B1

公开(公告)日：2018-01-02

申请号：US15197524

申请日：2016-06-29

Applicant: QUALCOMM Incorporated

Inventor： Percy Tehmul Marfatia ,  Rajagopal Narayanan ,  Shih-Hsin Jason Hu ,  Nan Chen

IPC: G11C11/00 ,  G06F13/16 ,  G11C11/417 ,  G11C7/22 ,  G11C7/04 ,  G11C7/10

CPC classification number: G06F13/1689 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/227 ,  G11C11/417

Abstract: An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configured to adjust an operating parameter of the memory based on the sensor emulating the portion of the timing circuit. A method is presented. The method includes at least operating a timing circuit to emulate a first operation of the memory, activating a second operation of the memory based on the emulating the first operation of the memory, emulating, by a sensor, a portion of the timing circuit. Another apparatus is presented. The apparatus includes at least a memory, a timing circuit, and means for tracking a performance of the memory based on the timing circuit tracking a memory operation.

公开(公告)号：US09575095B2

公开(公告)日：2017-02-21

申请号：US14459208

申请日：2014-08-13

Applicant: QUALCOMM Incorporated

Inventor： Junmou Zhang ,  Chuang Zhang ,  Yuancheng Christopher Pan ,  Nan Chen

IPC: G01R23/02 ,  G01R19/00 ,  G01R31/28 ,  G01R19/165

CPC classification number: G01R19/0084 ,  G01R19/16552 ,  G01R23/02 ,  G01R31/282

Abstract: Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.

Abstract translation: 本文描述了用于感测芯片上的电压的系统和方法。 在一个实施例中，电压传感器包括耦合到被感测的电压的压控振荡器和多个转换检测器，其中每个转换检测器耦合到振荡器上的不同位置，并且其中每个转换检测器 被配置为在一段时间段内对相应位置的多个转换进行计数。 电压传感器还包括加法器，其被配置为将来自转换检测器的转移数目相加以产生大致与电压成比例的输出值。

公开(公告)号：US09305632B2

公开(公告)日：2016-04-05

申请号：US13901511

申请日：2013-05-23

Applicant: QUALCOMM Incorporated

Inventor： Zeeshan Shafaq Syed ,  Nan Chen ,  Yong Xu ,  Michael Thomas Fertsch ,  Boris Dimitrov Andreev ,  Zhiqin Chen ,  Chang Ki Kwon

IPC: G06F1/32 ,  G11C11/4074

CPC classification number: G11C11/4074 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Abstract translation: 提供了一种方法和装置。 该装置是控制多个模块的功率模式的硬件模块。 该装置接收到期望的操作频率的指示。 基于接收到的指示，设备确定从与第一组模块相关联的第一功率模式切换到对应于期望操作频率并与第二组模块相关联的第二功率模式。 该装置使得与第一功率模式不相关的第二组模块中的模块在启用与第一功率模式不相关的第二组模块中的模块之后的一段时间期满后停止通过多个模块的业务 通过第二组模块路由流量，并禁用与第二功率模式无关的第一组模块中的模块。

公开(公告)号：US20160069939A1

公开(公告)日：2016-03-10

申请号：US14480321

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Chuang Zhang ,  Nan Chen ,  Junmou Zhang

IPC: G01R19/252 ,  G01R23/10

CPC classification number: G01R19/252 ,  G01R23/10 ,  H03M1/0607 ,  H03M1/1295 ,  H03M1/60

Abstract: In one embodiment, a method for measuring current comprises generating a sensor current based on a current being measured. The method also comprises converting a combined current into a first frequency, wherein the combined current is a sum of the sensor current and a common-mode current, and converting the first frequency into a first count value. The method further comprises converting the common-mode current into a second frequency, converting the second frequency into a second count value, and subtracting the second count value from the first count value to obtain a current reading.

Abstract translation: 在一个实施例中，用于测量电流的方法包括基于正被测量的电流产生传感器电流。 该方法还包括将组合电流转换成第一频率，其中组合电流是传感器电流和共模电流之和，并将第一频率转换为第一计数值。 该方法还包括将共模电流转换成第二频率，将第二频率转换成第二计数值，并从第一计数值减去第二计数值以获得电流读数。

公开(公告)号：US20160047847A1

公开(公告)日：2016-02-18

申请号：US14459208

申请日：2014-08-13

Applicant: QUALCOMM Incorporated

Inventor： Junmou Zhang ,  Chuang Zhang ,  Yuancheng Christopher Pan ,  Nan Chen

IPC: G01R19/00 ,  G01R23/02 ,  G01R31/28

CPC classification number: G01R19/0084 ,  G01R19/16552 ,  G01R23/02 ,  G01R31/282

Abstract: Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.

Abstract translation: 本文描述了用于感测芯片上的电压的系统和方法。 在一个实施例中，电压传感器包括耦合到被感测的电压的压控振荡器和多个转换检测器，其中每个转换检测器耦合到振荡器上的不同位置，并且其中每个转换检测器 被配置为在一段时间段内对相应位置的多个转换进行计数。 电压传感器还包括加法器，其被配置为将来自转换检测器的转移数目相加以产生大致与电压成比例的输出值。

公开(公告)号：US09213487B2

公开(公告)日：2015-12-15

申请号：US14055761

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Narasimhan Vasudevan ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0671 ,  G06F13/1668 ,  G11C7/10 ,  Y02D10/14

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract translation: 本文描述了用于存储器读取的接收器架构。 在一个实施例中，存储器接口包括多个发射器，其中多个发射器中的每一个被配置成通过多个I / O通道中的相应一个发射数据到存储器装置。 所述存储器接口还包括多个接收器，其中所述多个接收器中的每一个接收器耦合到所述多个发射器中的相应一个，并且被配置为通过所述多个I / O中的相应一个I / O从所述存储器装置接收数据 频道 多个接收机被分组在一起，位于远离多个发射机的接收机子系统中。

公开(公告)号：US09024684B2

公开(公告)日：2015-05-05

申请号：US13831639

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Nan Chen

IPC: H03B1/00 ,  H03K5/00 ,  H04B1/10 ,  H03L7/08 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03L7/0802 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/093

Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.

Abstract translation: 本文描述了用于降低锁相环（PLL）的环路滤波器中的噪声和功耗的技术。 在一个实施例中，用于PLL的环路滤波器包括第一比例电容器，第二比例电容器，有源器件和多个开关。 多个开关被配置为将第一比例电容器和第二比例电容器交替地耦合到第一电荷泵，以将来自有源器件的噪声交替耦合到第一比例电容器和第二比例电容器，并且交替地耦合第一比例电容器 电容器和第二比例电容器组成反馈电路，其中反馈电路产生环路滤波器的输出电压。