公开(公告)号：US20150221560A1

公开(公告)日：2015-08-06

申请号：US14686828

申请日：2015-04-15

Applicant: Renesas Electronics Corporation

Inventor： Katsuyuki HORITA ,  Toshiaki IWAMATSU ,  Hideki MAKIYAMA ,  Yoshiki YAMAMOTO

IPC: H01L21/84 ,  H01L21/768 ,  H01L21/28 ,  H01L21/283 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/84 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/486 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

Abstract translation: 提高了半导体器件的特性。 本发明的半导体器件包括：（a）布置在由元件隔离区包围的半导体区域形成的有源区中的MISFET; 和（b）布置在有源区下方的绝缘层。 此外，半导体器件包括：（c）布置在有源区下方以插入绝缘层的p型半导体区域; 和（d）布置在p型半导体区域下方的导电类型与p型相反的n型半导体区域。 并且，p型半导体区域包括从绝缘层的下方延伸的连接区域，并且MIS型的p型半导体区域和栅极电极通过作为一体形成的导电膜的共享插头彼此连接 从栅电极上方延伸到连接区域的上方。

公开(公告)号：US20130187230A1

公开(公告)日：2013-07-25

申请号：US13747537

申请日：2013-01-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract translation: 防止在SOI衬底上发生MOSFET的短沟道特性和寄生电容。 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。

公开(公告)号：US20190164764A1

公开(公告)日：2019-05-30

申请号：US16129549

申请日：2018-09-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki MAKIYAMA

IPC: H01L21/28 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/792 ,  H01L21/324

CPC classification number: H01L21/28202 ,  H01L21/28238 ,  H01L21/324 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/792

Abstract: Reliability of a semiconductor device is improved. In a method of manufacturing a semiconductor device, nitrogen is introduced into a surface of a substrate and a sacrificial film is formed on the surface in a field effect transistor formation region different from a memory transistor formation region. Subsequently, the sacrificial film is removed to remove the nitrogen introduced in the surface of the substrate in the field effect transistor formation region.

公开(公告)号：US20190043949A1

公开(公告)日：2019-02-07

申请号：US16150323

申请日：2018-10-03

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/08 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/74 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/768 ,  H01L29/423 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20180219067A1

公开(公告)日：2018-08-02

申请号：US15925850

申请日：2018-03-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/74 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20180019315A1

公开(公告)日：2018-01-18

申请号：US15717397

申请日：2017-09-27

Applicant: Renesas Electronics Corporation

Inventor： Hideki MAKIYAMA

IPC: H01L29/49 ,  H01L27/12 ,  H01L23/522 ,  H01L21/265 ,  H01L21/84 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L29/66 ,  H01L21/66

CPC classification number: H01L29/4983 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/84 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L23/5226 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an offset spacer film formed over the side wall surface of a gate electrode of an SOTB transistor STR, etc. When the measured thickness is within the tolerance of a standard thickness, standard implantation energy and a standard dose amount are set. When the measured thickness is smaller than the standard thickness, implantation energy and a dose amount, which are respectively lower than the standard values thereof, are set. When the measured thickness is larger than the standard thickness, implantation energy and a dose amount, which are respectively higher than the standard values thereof, are set.

公开(公告)号：US20170352687A1

公开(公告)日：2017-12-07

申请号：US15603564

申请日：2017-05-24

Applicant: Renesas Electronics Corporation

Inventor： Hideki MAKIYAMA

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L27/1207 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649

Abstract: A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed.

公开(公告)号：US20170018611A1

公开(公告)日：2017-01-19

申请号：US15279565

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract translation: 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。

公开(公告)号：US20160013207A1

公开(公告)日：2016-01-14

申请号：US14794105

申请日：2015-07-08

Applicant: Renesas Electronics Corporation

Inventor： Hideki MAKIYAMA

IPC: H01L27/12 ,  H01L29/423 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/78648

Abstract: A semiconductor device including an SOI substrate reduces a gate leak current of an anti-antenna-effect dummy fill-cell and suppresses an antenna effect. The thickness of a gate insulating film of the anti-antenna-effect dummy fill-cell is determined to be large than that of a gate insulating film of an SOI transistor. This reduces the gate leak current of the anti-antenna-effect dummy fill-cell. The gate area (gate length×gate width) of the anti-antenna-effect dummy fill-cell is determined to be large than that (gate length×gate width) of the SOI transistor. This makes the gate capacity of the anti-antenna-effect dummy fill-cell almost equal to that of SOI transistor, thereby suppressing the antenna effect.

Abstract translation: 包括SOI衬底的半导体器件减少了反天线效应虚拟填充单元的栅极漏电流并且抑制了天线效应。 反天线效应虚拟填充单元的栅极绝缘膜的厚度被确定为大于SOI晶体管的栅极绝缘膜的厚度。 这降低了反天线效应虚拟充电单元的栅极漏电流。 反天线效应虚拟填充单元的栅极面积（栅极长度×栅极宽度）被确定为大于SOI晶体管的栅极长度（栅极长度×栅极宽度）。 这使得反天线效应虚拟填充单元的栅极容量几乎等于SOI晶体管的栅极容量，从而抑制天线效应。

公开(公告)号：US20130140669A1

公开(公告)日：2013-06-06

申请号：US13691800

申请日：2012-12-02

Applicant: Renesas Electronics Corporation

Inventor： Jiro YUGAMI ,  Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA ,  Yasuo INOUE ,  Yoshiki YAMAMOTO

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649

Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.

Abstract translation: 在SOI衬底上形成作为半导体元件的第一MISFET。 SOI衬底包括作为基底的支撑衬底，BOX层，其是形成在支撑衬底的主表面（表面）上的绝缘层，即掩埋氧化物膜; 以及作为在BOX层上形成的半导体层的SOI层。 作为半导体元件的第一MISFET形成于SOI层。 在隔离区域中，穿过SOI层和BOX层形成隔离槽，使得槽的底面位于支撑基板的厚度的中间。 隔离膜被埋在正在形成的隔离槽中。 然后，在BOX层和隔离膜之间插入抗氧化膜。