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127 条记录 (耗时 0.024 秒)

    SPLIT GATE MEMORY CELL METHOD
    21.
    发明申请
    SPLIT GATE MEMORY CELL METHOD 有权
    分离栅存储单元方法

    公开(公告)号：US20080182375A1

    公开(公告)日：2008-07-31

    申请号：US11669307

    申请日：2007-01-31

    申请人： Rajesh Rao ,  Ramachandran Muralidhar ,  Leo Mathew

    发明人： Rajesh Rao ,  Ramachandran Muralidhar ,  Leo Mathew

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7923 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7887

    摘要： A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer. A first sidewall spacer is formed adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer. The pillar is replaced with a select gate. The area of reduced thickness is selectively removed to leave the first and second portions as control gates.

    摘要翻译： 在衬底上形成多位分离栅极存储器件。 在衬底上形成存储层。 在存储层上形成第一导电层。 去除导电层的一部分的厚度以留下导电层的柱和导电层的厚度减小的面积。 形成邻近柱的第一侧壁间隔物以覆盖导电层厚度减小区域的第一部分和第二部分。 柱子被一个选择门取代。 选择性地去除厚度减小的区域以留下第一和第二部分作为控制门。

    LIGHT ERASABLE MEMORY AND METHOD THEREFOR
    22.
    发明申请
    LIGHT ERASABLE MEMORY AND METHOD THEREFOR 有权
    光可擦除存储器及其方法

    公开(公告)号：US20080164512A1

    公开(公告)日：2008-07-10

    申请号：US11620075

    申请日：2007-01-05

    申请人： Rajesh A. Rao ,  Leo Mathew ,  Ramachandran Muralidhar ,  Bruce E. White

    发明人： Rajesh A. Rao ,  Leo Mathew ,  Ramachandran Muralidhar ,  Bruce E. White

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  H01L21/84 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11517 ,  H01L27/1203 ,  H01L27/15 ,  H01L29/66825 ,  H01L29/788

    摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.

    摘要翻译： 半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。 互连层在半导体层之上。 存储器阵列位于顶部半导体层部分和互连层的一部分中。 通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。 结果是存储器阵列从背面接收光并被擦除。

    Semiconductor device having nano-pillars and method therefor
    23.
    发明申请
    Semiconductor device having nano-pillars and method therefor 有权
    具有纳米柱的半导体器件及其方法

    公开(公告)号：US20070082495A1

    公开(公告)日：2007-04-12

    申请号：US11244516

    申请日：2005-10-06

    申请人： Leo Mathew ,  Rajesh Rao ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Rajesh Rao ,  Ramachandran Muralidhar

    IPC分类号： H01L29/76 ,  H01L21/461 ,  H01L21/302 ,  H01L29/745

    CPC分类号： H01L29/42368 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/32139 ,  H01L28/91 ,  H01L29/512 ,  H01L29/513

    摘要： A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.

    摘要翻译： 半导体器件包括由导电材料形成的多个支柱。 通过使用多个纳米晶体作为用于图案化导电材料的硬掩模来形成柱。 导电材料的厚度决定了支柱的高度。 同样，柱的宽度由纳米晶体的直径决定。 在一个实施例中，柱由多晶硅形成，并且用作具有良好电荷保持和低电压操作的非易失性存储单元的电荷存储区。 在另一个实施例中，支柱由金属形成，并且用作具有增加的电容的金属 - 绝缘体 - 金属（MIM）电容器的平板电极，而不增加集成电路的表面积。

    Non-volatile memory cell including a capacitor structure and processes for forming the same
    24.
    发明申请
    Non-volatile memory cell including a capacitor structure and processes for forming the same 有权
    包括电容器结构的非易失性存储单元及其形成方法

    公开(公告)号：US20060220102A1

    公开(公告)日：2006-10-05

    申请号：US11083878

    申请日：2005-03-18

    申请人： Leo Mathew ,  Ramachandran Muralidhar ,  Tab Stephens

    发明人： Leo Mathew ,  Ramachandran Muralidhar ,  Tab Stephens

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

    摘要： A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.

    摘要翻译： 非易失性存储单元可以包括衬底，覆盖衬底的有源区和覆盖衬底的电容器结构。 从平面图，电容器结构围绕有源区域。 在一个实施例中，非易失性存储单元包括浮置栅电极和控制栅电极。 电容器结构包括第一电容器部分，第一电容器部分包括第一电容器电极和第二电容器电极。 第一电容器电极电连接到浮置栅电极，并且第二电容器电极电连接到控制栅电极。 用于形成非易失性存储单元的方法可以包括在衬底上形成有源区，并在衬底上形成电容器结构，其中从平面图看，电容器结构围绕有源区。

    Transistor with vertical dielectric structure
    25.
    发明申请
    Transistor with vertical dielectric structure 有权
    具有垂直电介质结构的晶体管

    公开(公告)号：US20050282345A1

    公开(公告)日：2005-12-22

    申请号：US10871772

    申请日：2004-06-18

    申请人： Leo Mathew ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Ramachandran Muralidhar

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788

    CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7887

    摘要： A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure and a portion laterally adjacent to the dielectric structure. In one embodiment, the gate structure is a floating gate structure wherein a control gate structure (719) also includes portion laterally adjacent to the dielectric structure and a portion laterally adjacent to the semiconductor structure. In some examples, having a portion of the floating gate and a portion of the control gate adjacent to the dielectric structure acts to increase the control gate to floating gate capacitance without significantly increasing the capacitance of the floating gate to channel region.

    摘要翻译： 一种具有垂直结构（113）的晶体管（103），其包括半导体结构（109）下面的电介质结构（201）。 半导体结构包括沟道区（731）和源极/漏极区（707,709）。 晶体管包括具有与半导体结构横向相邻的部分和与电介质结构横向相邻的部分的栅极结构（705,703）。 在一个实施例中，栅极结构是浮动栅极结构，其中控制栅极结构（719）还包括横向邻近电介质结构的部分和与半导体结构横向相邻的部分。 在一些示例中，具有浮置栅极的一部分和与电介质结构相邻的控制栅极的一部分用于将控制栅极增加到浮置栅极电容，而不显着增加浮置栅极到沟道区的电容。

    Transistor having three electrically isolated electrodes and method of formation
    27.
    发明申请
    Transistor having three electrically isolated electrodes and method of formation 有权
    具有三个电隔离电极的晶体管和形成方法

    公开(公告)号：US20050098822A1

    公开(公告)日：2005-05-12

    申请号：US10705317

    申请日：2003-11-10

    申请人： Leo Mathew ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Ramachandran Muralidhar

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76

    CPC分类号： H01L27/108 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881

    摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

    摘要翻译： 晶体管（10）形成有三个可分别控制的栅极（44,42,18）。 三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。 通道侧壁上的电介质可以不同于通道顶部的电介质。 选择性地制造到源极，漏极和三个栅极的电接触。 通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。 当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。 当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。