公开(公告)号：US20160190294A1

公开(公告)日：2016-06-30

申请号：US14961545

申请日：2015-12-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/42368 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/66462 ,  H01L29/7786

Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.

Abstract translation: 为了提高半导体器件的特性，包括：形成在衬底上的沟道层和势垒层; 以及通过栅极绝缘膜布置在势垒层上的栅电极，该半导体器件被配置如下。 氮化硅膜设置在源电极和栅电极之间的阻挡层上方，并且还设置在漏电极和栅电极GE之间的阻挡层上。 阻挡层的表面电位被氮化硅膜还原，从而形成二维电子气。 因此，通过仅在形成氮化硅膜的区域中选择性地形成二维电子气，即使不采用沟槽栅极结构，也可以进行常关断操作。

公开(公告)号：US20240204098A1

公开(公告)日：2024-06-20

申请号：US18592332

申请日：2024-02-29

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20210074816A1

公开(公告)日：2021-03-11

申请号：US16996351

申请日：2020-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20180342589A1

公开(公告)日：2018-11-29

申请号：US15966773

申请日：2018-04-30

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Tatsuo NAKAYAWA ,  Yasuhiro OKAMOTO ,  Atsushi TSUBOI

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/2003 ,  H01L21/0262 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/432 ,  H01L29/513 ,  H01L29/66462 ,  H01L29/7783

Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.

公开(公告)号：US20170005189A1

公开(公告)日：2017-01-05

申请号：US15265328

申请日：2016-09-14

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, a gate electrode formed over the third semiconductor layer, and a gate insulating film formed between the third semiconductor layer and the gate electrode. The second semiconductor layer includes an Alyα1-yN layer (α includes Ga or In, and 0≦y y” at an interface between the second nitride semiconductor layer and the third nitride semiconductor layer.

Abstract translation: 半导体器件包括第一半导体层，形成在第一半导体层上的第二半导体层，形成在第二半导体层上的第三半导体层，形成在第三半导体层上的栅电极和形成在第三半导体层之间的栅极绝缘膜 半导体层和栅电极。 第二半导体层包括Alyα1-yN层（α包括Ga或In，并且0≤y<1），第三半导体层包括Alzα1-zN层（0≤z<1）。 形成第二半导体层的Alyα1-yN层的y至少在栅极下方的区域从第三半导体层增加到第一半导体层。 在第二氮化物半导体层和第三氮化物半导体层之间的界面处存在关系“z> y”。

公开(公告)号：US20160204243A1

公开(公告)日：2016-07-14

申请号：US15079879

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Takashi INOUE ,  Toshiyuki TAKEWAKI ,  Tatsuo NAKAYAMA ,  Yasuhiro OKAMOTO ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L23/31 ,  H01L29/205 ,  H01L23/29 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/518 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.

公开(公告)号：US20160064538A1

公开(公告)日：2016-03-03

申请号：US14837053

申请日：2015-08-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/15 ,  H01L29/66 ,  H01L29/207 ,  H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Abstract translation: 改善了半导体器件的特性。 半导体器件具有在衬底上形成的含有ap型杂质，沟道层和阻挡层的电位固定层，以及布置在穿过势垒层的沟槽中的栅极，并且通过沟道层的某一点通过 门绝缘膜。 源极和漏极形成在栅电极的相对侧上。 含p型杂质的电位固定层在栅电极和漏电极之间具有含有诸如氢之类的钝化元件的失活区域。 因此，在提高源电极侧的电位固定层的p型杂质（受体）浓度的同时，在漏电极侧使电位固定层的p型杂质失活。 这可以提高漏极侧击穿电压，同时通过p型杂质提供电荷的去除效果。

公开(公告)号：US20140015019A1

公开(公告)日：2014-01-16

申请号：US13937846

申请日：2013-07-09

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Takashi INOUE ,  Tatsuo NAKAYAMA ,  Ryohei NEGA ,  Masaaki KANAZAWA ,  Hironobu MIYAMOTO

IPC: H01L29/78

CPC classification number: H01L29/452 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.

Abstract translation: 提高了由氮化物半导体材料制成的场效应晶体管的可靠性。 欧姆电极包括被隔离以彼此分离的多个单元电极。 由此，能够防止在y轴方向（负方向）在单位电极中流通导通电流。 此外，在各单元电极中，可以防止沿y轴方向（负方向）流动的通态电流的电流密度增加。 结果，可以提高欧姆电极的电迁移电阻。

公开(公告)号：US20230369414A1

公开(公告)日：2023-11-16

申请号：US18358474

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/66734 ,  H01L29/7813

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20230027022A1

公开(公告)日：2023-01-26

申请号：US17828376

申请日：2022-05-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehirou MARIKO ,  Yasuhiro OKAMOTO ,  Senichirou NAGASE

IPC: H01L23/544 ,  H01L29/06 ,  H01L29/78 ,  H01L21/66 ,  H01L21/304 ,  H01L21/78

Abstract: In a semiconductor device in a wafer state, an element region and a scribe region are defined in one main surface of a semiconductor substrate. In the element region, a vertical MOS transistor is formed as a semiconductor element. In the scribe region, an n-type column region and a p-type column region are defined. An n-type column resistor is formed in the n-type column region. A p-type column resistor is formed in the p-type column region.