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45 条记录 (耗时 0.034 秒)

    STRUCTURE AND METHOD TO FABRICATE MOSFET WITH SHORT GATE
    21.
    发明申请
    STRUCTURE AND METHOD TO FABRICATE MOSFET WITH SHORT GATE 有权
    具有短栅的MOSFET的结构和方法

    公开(公告)号：US20090184378A1

    公开(公告)日：2009-07-23

    申请号：US12016317

    申请日：2008-01-18

    申请人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    发明人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

    摘要： A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

    摘要翻译： 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

    Structure and method to fabricate MOSFET with short gate
    24.
    发明授权
    Structure and method to fabricate MOSFET with short gate 有权
    用短栅制造MOSFET的结构和方法

    公开(公告)号：US07943467B2

    公开(公告)日：2011-05-17

    申请号：US12016317

    申请日：2008-01-18

    申请人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    发明人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

    摘要： A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

    摘要翻译： 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

    METHOD TO REDUCE PLASMA CHARGE DAMAGE FROM HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP-CVD) PROCESS
    25.
    发明申请
    METHOD TO REDUCE PLASMA CHARGE DAMAGE FROM HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP-CVD) PROCESS 审中-公开
    降低高密度等离子体化学气相沉积（HDP-CVD）工艺的等离子体电荷损失的方法

    公开(公告)号：US20080146039A1

    公开(公告)日：2008-06-19

    申请号：US11611212

    申请日：2006-12-15

    申请人： Daewon Yang ,  Jeffery B. Maxson ,  Ann N. McDonald

    发明人： Daewon Yang ,  Jeffery B. Maxson ,  Ann N. McDonald

    IPC分类号： H01L21/283

    CPC分类号： C23C16/50

    摘要： A method of processing wafers within a high density plasma chemical vapor deposition chamber comprises setting a plasma charge level within the chamber at a zero power level and, while the plasma charge level within the chamber is at the zero power level, moving a wafer into the chamber. Then, the method sets the plasma charge level to a second power level higher than zero after the wafer is moved into the chamber and performs a chemical vapor deposition process on the wafer within the chamber. After performing the chemical vapor deposition process, the method moves the wafer to a non-plasma region within the chamber. Then, after moving the wafer to the non-plasma region within the chamber, the method again sets the plasma charge level within the chamber at the zero power level. Next, after setting the plasma charge level within the chamber at the zero power level, the method opens the door of the chamber and, while the plasma charge level within the chamber is at the zero power level, the method removes the wafer from the chamber through the door of the chamber.

    摘要翻译： 在高密度等离子体化学气相沉积室内处理晶片的方法包括在零功率水平下设置室内的等离子体电荷水平，并且在室内的等离子体电荷水平处于零功率水平的同时，将晶片移动到 房间。 然后，该方法将晶片移入腔室之后，将等离子体电荷电平设置为高于零的第二功率电平，并在腔室内的晶片上执行化学气相沉积工艺。 在执行化学气相沉积工艺之后，该方法将晶片移动到室内的非等离子体区域。 然后，在将晶片移动到室内的非等离子体区域之后，该方法再次将室内的等离子体电荷水平设置在零功率水平。 接下来，在将腔室内的等离子体充电水平设置在零功率水平之后，该方法打开腔室的门，并且在室内的等离子体充电水平处于零功率水平的同时，该方法将晶片从腔室 通过房间的门。

    CMOS structures and methods using self-aligned dual stressed layers
    28.
    发明授权
    CMOS structures and methods using self-aligned dual stressed layers 失效
    CMOS结构和方法采用自对准双应力层

    公开(公告)号：US07521307B2

    公开(公告)日：2009-04-21

    申请号：US11380695

    申请日：2006-04-28

    申请人： Huilong Zhu ,  Daewon Yang

    发明人： Huilong Zhu ,  Daewon Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/31116 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/7843

    摘要： A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact to a silicide layer upon a source/drain region within one of the first transistor and the second transistor.

    摘要翻译： 用于制造CMOS结构的CMOS结构和方法提供了位于第一晶体管之上的第一应力层和位于第二晶体管上方的第二应力层邻接但不重叠。 当在第一晶体管和第二晶体管之一内的源极/漏极区域上形成与硅化物层的接触时，这种不存在重叠的基台提供增强的制造灵活性。

    Compressive nitride film and method of manufacturing thereof
    29.
    发明授权
    Compressive nitride film and method of manufacturing thereof 有权
    压缩性氮化物膜及其制造方法

    公开(公告)号：US07514370B2

    公开(公告)日：2009-04-07

    申请号：US11419217

    申请日：2006-05-19

    申请人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

    发明人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

    摘要翻译： 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。