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    Semiconductor memory device
    21.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07933141B2

    公开(公告)日：2011-04-26

    申请号：US12416432

    申请日：2009-04-01

    申请人： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Yasutoshi Yamada

    发明人： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Yasutoshi Yamada

    IPC分类号： G11C11/24

    CPC分类号： G11C5/147 ,  G11C7/04 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

    摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.

    摘要翻译： 在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。 本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。 监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过以下方式适当地执行对存储器单元的重新加载操作： 全局局部感测放大器。 因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。

    Semiconductor memory device
    22.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07903449B2

    公开(公告)日：2011-03-08

    申请号：US12485568

    申请日：2009-06-16

    申请人： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Yasutoshi Yamada

    发明人： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Yasutoshi Yamada

    IPC分类号： G11C11/24

    CPC分类号： G11C7/02 ,  G11C11/4074 ,  G11C11/4099 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

    摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.

    摘要翻译： 半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。 每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。 电容器的第一电极连接到存储单元中的晶体管。 虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。 虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。 虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。

    SEMICONDUCTOR MEMORY DEVICE
    23.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20090323399A1

    公开(公告)日：2009-12-31

    申请号：US12485568

    申请日：2009-06-16

    申请人： Kazuhiko KAJIGAYA ,  Soichiro Yoshida ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Yasutoshi Yamada

    发明人： Kazuhiko KAJIGAYA ,  Soichiro Yoshida ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Yasutoshi Yamada

    IPC分类号： G11C11/24 ,  G11C8/08 ,  H01L27/108

    CPC分类号： G11C7/02 ,  G11C11/4074 ,  G11C11/4099 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

    摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.

    摘要翻译： 半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。 每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。 电容器的第一电极连接到存储单元中的晶体管。 虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。 虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。 虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。

    Semiconductor memory device capable of canceling out noise development
    24.
    发明申请
    Semiconductor memory device capable of canceling out noise development 审中-公开
    能够消除噪声发展的半导体存储器件

    公开(公告)号：US20070297257A1

    公开(公告)日：2007-12-27

    申请号：US11889902

    申请日：2007-08-17

    申请人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

    发明人： Tomonori Sekiguchi ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Riichiro Takemura ,  Tsugio Takahashi ,  Yoshitaka Nakamura

    IPC分类号： G11C7/02

    CPC分类号： G11C7/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10897

    摘要： A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor and a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.

    摘要翻译： 动态RAM包含多个动态存储单元，每个动态存储单元包括具有作为选择端子的栅极集合的MOSFET，作为输入/输出端子的一个源极和漏极组，以及连接到电容器的存储节点的另一个源极和漏极 以及电容器，分别连接到多个动态存储单元的选择端子的多个字线，分别连接到多个动态存储单元的输入/输出端子的多个互补位线对，以及读出放大器 阵列包括多个锁存电路，其分别放大互补位线对之间的电压差，以便从每对输入/输出端子彼此相反的方向延伸。 电源线以网格形式提供，包括字驱动器上方的一部分。

    Semiconductor memory device
    25.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06992343B2

    公开(公告)日：2006-01-31

    申请号：US10975494

    申请日：2004-10-29

    申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

    摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

    摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期来实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/比特方法的DRAM具有采用单交叉6F 单元的双单元结构，其结构是：将存储单元布置在与 位线对和字线之间的交点; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。 此外，在硅衬底中形成每个存储单元的晶体管的源极，沟道和漏极的有源区相对于位线对的方向倾斜地形成。

    Semiconductor memory device
    27.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06882557B2

    公开(公告)日：2005-04-19

    申请号：US10656351

    申请日：2003-09-05

    申请人： Kazuhiko Kajigaya ,  Hiromasa Noda ,  Shinichi Miyatake ,  Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

    发明人： Kazuhiko Kajigaya ,  Hiromasa Noda ,  Shinichi Miyatake ,  Riichiro Takemura ,  Tomonori Sekiguchi ,  Takeshi Sakata

    IPC分类号： H01L21/8242 ,  G11C5/06 ,  G11C7/18 ,  G11C11/22 ,  G11C11/401 ,  G11C11/4097 ,  G11C29/50 ,  H01L27/02 ,  H01L27/108

    CPC分类号： G11C29/50 ,  G11C7/18 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/10897

    摘要： The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased.The switches are connected to one-side ends of the bit lines provided at the odd-numbered positions, and are connected to the other-side ends of the bit lines provided at the even-numbered positions. A pair of odd-numbered or even-numbered bit lines are connected to the terminals of each sense amplifier, respectively. The memory cells are arranged at predetermined intersection points of the word lies and the bit lines, the number of the predetermined intersection points being equal to half of all the intersection points thereof, in such a manner that when one word line is selected, the memory cells connected to the selected word-line can be electrically connected in such a manner that one memory cell is electrically connected to each terminal of the unit circuits.

    摘要翻译： 每个开关的接触电阻减小，并且所有开关的导通电阻被设置为均匀，而位线选择开关的布置所需的面积不增加。 开关连接到设置在奇数位置的位线的一侧端子，并连接到设置在偶数位置的位线的另一端。 一对奇数或偶数位线分别连接到每个读出放大器的端子。 存储单元被布置在字位置和位线的预定交点处，预定交点的数量等于其所有交点的一半，使得当选择一个字线时，存储器 连接到所选字线的单元可以以一个存储单元电连接到单元电路的每个端子的方式电连接。

    Semiconductor device
    29.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US06671198B2

    公开(公告)日：2003-12-30

    申请号：US10354122

    申请日：2003-01-30

    申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

    发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

    IPC分类号： G11C506

    CPC分类号： H01L27/10894 ,  G11C11/4097 ,  H01L27/10897

    摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.