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112 条记录 (耗时 0.033 秒)

    Vertical-type non-volatile memory devices
    21.
    发明授权
    Vertical-type non-volatile memory devices 有权
    垂直型非易失性存储器件

    公开(公告)号：US08492828B2

    公开(公告)日：2013-07-23

    申请号：US13567299

    申请日：2012-08-06

    申请人： Yong-Hoon Son ,  Jong-Wook Lee

    发明人： Yong-Hoon Son ,  Jong-Wook Lee

    IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/068 ,  H01L31/119 ,  H01L31/113

    CPC分类号： H01L27/11568 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556

    摘要： In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

    摘要翻译： 在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。 提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。 单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案和垂直沟道之间，使栅极图案与垂直沟道绝缘 。

    Vertical type semiconductor device and method of manufacturing a vertical type semiconductor device
    22.
    发明授权
    Vertical type semiconductor device and method of manufacturing a vertical type semiconductor device 有权
    垂直型半导体器件及其制造方法

    公开(公告)号：US08324056B2

    公开(公告)日：2012-12-04

    申请号：US13317022

    申请日：2011-10-07

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/7827 ,  H01L29/66666

    摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

    摘要翻译： 垂直柱半导体器件可以包括衬底，沟道图案组，栅极绝缘层图案和栅电极。 衬底可分为有源区和隔离层。 可以在对应于有源区的衬底中形成第一杂质区。 通道图案组可以从有源区域的表面突出并且可以彼此平行地布置。 第二杂质区可以形成在沟道图案组的上部。 栅极绝缘层图案可以形成在衬底和沟道图案组的侧壁上。 栅极绝缘层图案可以与沟道图案组的上表面间隔开。 栅电极可以接触栅极绝缘层并且可以包围沟道图案组的侧壁。

    Vertical type semiconductor device and method of manufacturing a vertical type semiconductor device
    26.
    发明申请
    Vertical type semiconductor device and method of manufacturing a vertical type semiconductor device 有权

    公开(公告)号：US20120028428A1

    公开(公告)日：2012-02-02

    申请号：US13317022

    申请日：2011-10-07

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7827 ,  H01L29/66666

    摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

    Integrated circuit devices including a transcription-preventing pattern
    29.
    发明授权
    Integrated circuit devices including a transcription-preventing pattern 失效
    集成电路装置，包括转录阻止图案

    公开(公告)号：US07816735B2

    公开(公告)日：2010-10-19

    申请号：US11974293

    申请日：2007-10-12

    申请人： Pil-Kyu Kang ,  Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee ,  Byeong-Chan Lee ,  InSoo Jung

    发明人： Pil-Kyu Kang ,  Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee ,  Byeong-Chan Lee ,  InSoo Jung

    IPC分类号： H01L33/16

    CPC分类号： H01L21/823425 ,  H01L21/823475

    摘要： Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.

    摘要翻译： 在第一单晶层上提供包括第一单晶层和绝缘层图案的集成电路器件。 绝缘层图案在其中具有部分地暴露第一单晶层的开口。 种子层在开口处。 第二单晶层位于绝缘层图案和籽晶层上。 第二单晶层具有与种子层基本相同的晶体结构。 转录阻止图案位于转录阻止图案和第二单晶层上的第二单晶层和第三单晶层上。 转录阻止图案被配置为将第二单晶层中的缺陷部分的转录限制为第三单晶层。

    Methods of laterally forming single crystalline thin film regions from seed layers
    30.
    发明授权
    Methods of laterally forming single crystalline thin film regions from seed layers 失效
    从种子层横向形成单晶薄膜区域的方法

    公开(公告)号：US07700461B2

    公开(公告)日：2010-04-20

    申请号：US12061253

    申请日：2008-04-02

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee ,  Pil-Kyu Kang

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee ,  Pil-Kyu Kang

    IPC分类号： H01L21/20

    CPC分类号： H01L21/8221 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02667 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1285 ,  H01L29/78675

    摘要： In a method of manufacturing a semiconductor device, a string structure including a selection transistor and a memory cell on a substrate. An insulation layer pattern is formed on the substrate to cover the string structure. The insulation layer pattern includes at least one opening exposing a portion of the substrate adjacent to the selection transistor. A seed layer including a single-crystalline material is formed in the opening. An amorphous thin film including an amorphous material is formed on the insulation layer pattern and the seed layer. The amorphous thin film is transformed into a single-crystalline thin film, using the single-crystalline material in the seed layer as a seed during a phase transition of the amorphous thin film, to form a channel layer on the insulation layer pattern and the seed layer. Therefore, the semiconductor device including the channel layer having the single-crystalline thin film may be manufactured.

    摘要翻译： 在制造半导体器件的方法中，包括在衬底上的选择晶体管和存储单元的串联结构。 在衬底上形成绝缘层图案以覆盖串结构。 绝缘层图案包括暴露基板的与选择晶体管相邻的部分的至少一个开口。 在开口中形成包括单晶材料的晶种层。 在绝缘层图案和种子层上形成包含非晶材料的非晶态薄膜。 在非晶薄膜的相变期间，将晶种层中的单晶材料作为种子，将非晶薄膜转变为单晶薄膜，以在绝缘层图案和种子上形成沟道层 层。 因此，可以制造包括具有单晶薄膜的沟道层的半导体器件。