利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

56 条记录 (耗时 0.031 秒)

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    24.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20080087943A1

    公开(公告)日：2008-04-17

    申请号：US11873104

    申请日：2007-10-16

    申请人： Minori Kajimoto

    发明人： Minori Kajimoto

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S257/90

    摘要： A nonvolatile semiconductor memory device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain region formed at each side of the gate electrode in the substrate, a first silicon oxide film formed on a gate electrode sidewall so as to serve as a spacer, the first silicon oxide film having a first lower surface in contact with the source/drain region and an upper surface located lower than the substrate upper surface, a second silicon oxide film formed on the source/drain region and a side surface of the first silicon oxide film, the second silicon oxide film having a second lower surface which is in contact with the substrate and is located lower than the lower surface of the first silicon oxide film, and a silicon nitride film formed on an upper surface of the second silicon oxide film.

    摘要翻译： 非易失性半导体存储器件包括形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在衬底中的栅电极的每一侧的源/漏区，形成在第一氧化硅膜上的第一氧化硅膜 栅电极侧壁作为间隔物，所述第一氧化硅膜具有与所述源极/漏极区域接触的第一下表面和位于比所述基板上表面低的上表面，形成在所述第二氧化硅膜上的第二氧化硅膜 源极/漏极区域和第一氧化硅膜的侧表面，第二氧化硅膜具有与基板接触并且位于比第一氧化硅膜的下表面低的第二下表面，以及硅 形成在第二氧化硅膜的上表面上的氮化物膜。

    Semiconductor device and method of manufacturing the same
    26.
    发明申请
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US20060244094A1

    公开(公告)日：2006-11-02

    申请号：US11412951

    申请日：2006-04-28

    申请人： Minori Kajimoto ,  Mitsuhiro Noguchi

    发明人： Minori Kajimoto ,  Mitsuhiro Noguchi

    IPC分类号： H01L29/00 ,  H01L21/4763

    CPC分类号： H01L27/105 ,  H01L21/76807 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/78

    摘要： A semiconductor device including a semiconductor substrate of a first conductive type; a first semiconductor region of the first conductive type formed on the semiconductor substrate; a second semiconductor region of a second conductive type formed on the semiconductor substrate; a low-threshold low-voltage transistor formed on the semiconductor substrate; a high-threshold low-voltage transistor formed on the first semiconductor substrate; the high-threshold low-voltage transistor and the low-threshold low-voltage transistors formed on the second semiconductor substrate; an element isolation region formed on the semiconductor substrate to isolate elements; wherein a transistor forming region of the low-threshold low-voltage transistor in the semiconductor substrate is surrounded by the first semiconductor region.

    摘要翻译： 一种半导体器件，包括第一导电类型的半导体衬底; 形成在半导体衬底上的第一导电类型的第一半导体区域; 形成在所述半导体衬底上的第二导电类型的第二半导体区域; 形成在半导体基板上的低阈值低压晶体管; 形成在第一半导体衬底上的高阈值低压晶体管; 形成在第二半导体衬底上的高阈值低压晶体管和低阈值低压晶体管; 形成在所述半导体衬底上以隔离元件的元件隔离区; 其中半导体衬底中的低阈值低压晶体管的晶体管形成区域被第一半导体区域包围。

    Nonvolatile semiconductor memory
    27.
    发明申请
    Nonvolatile semiconductor memory 有权
    非易失性半导体存储器

    公开(公告)号：US20050265109A1

    公开(公告)日：2005-12-01

    申请号：US11135415

    申请日：2005-05-24

    申请人： Akira Goda ,  Mitsuhiro Noguchi ,  Minori Kajimoto ,  Yuji Takeuchi

    发明人： Akira Goda ,  Mitsuhiro Noguchi ,  Minori Kajimoto ,  Yuji Takeuchi

    IPC分类号： H01L27/10 ,  G11C8/00 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521

    摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.

    摘要翻译： 非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和 栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。 字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离 字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。

    Nonvolatile semiconductor memory device with twin-well
    28.
    发明授权
    Nonvolatile semiconductor memory device with twin-well 失效
    具有双阱的非易失性半导体存储器件

    公开(公告)号：US08268686B2

    公开(公告)日：2012-09-18

    申请号：US13170592

    申请日：2011-06-28

    申请人： Mitsuhiro Noguchi ,  Minori Kajimoto

    发明人： Mitsuhiro Noguchi ,  Minori Kajimoto

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11546 ,  H01L27/105 ,  H01L27/11526

    摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.

    摘要翻译： 非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱 ，其包括围绕第一阱的侧部区域的第一部分和围绕第一阱的下部区域的第二部分，并且将第一阱与半导体衬底以及第二导电类型的第三阱电隔离， 其形成在半导体衬底中。 第三井具有比第二井的第二部分更少的深度。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    29.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20120217569A1

    公开(公告)日：2012-08-30

    申请号：US13365470

    申请日：2012-02-03

    申请人： Shigeru KINOSHITA ,  Hisataka Meguro ,  Minori Kajimoto

    发明人： Shigeru KINOSHITA ,  Hisataka Meguro ,  Minori Kajimoto

    IPC分类号： H01L29/788 ,  H01L21/28

    CPC分类号： H01L21/28273 ,  H01L29/42336 ,  H01L29/66825

    摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film.

    摘要翻译： 根据一个实施例，非易失性半导体存储器件包括衬底，隧道绝缘膜，浮动栅极，泄漏抑制单元，栅极间绝缘膜和控制栅极。 衬底包括硅。 隧道绝缘膜设置在基板上。 浮动栅极设置在隧道绝缘膜上。 泄漏抑制单元设置在浮动栅极上。 栅极间绝缘膜设置在泄漏抑制单元上。 控制栅极设置在栅极间绝缘膜上。 泄漏抑制单元的介电常数高于栅极间绝缘膜的介电常数。

    Semiconductor device manufacturing method
    30.
    发明授权
    Semiconductor device manufacturing method 失效
    半导体器件制造方法

    公开(公告)号：US07943478B2

    公开(公告)日：2011-05-17

    申请号：US12541457

    申请日：2009-08-14

    申请人： Haruhiko Koyama ,  Mitsuhiro Noguchi ,  Minori Kajimoto

    发明人： Haruhiko Koyama ,  Mitsuhiro Noguchi ,  Minori Kajimoto

    IPC分类号： H01L21/76

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/942 ,  Y10S438/975

    摘要： In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.

    摘要翻译： 在半导体器件制造方法中，包括半导体层的衬底结构的表面被包括第一和第二开口的第一膜覆盖。 第一开口被配置为对准标记。 第二开口被构造为用于将杂质引入半导体层的第一预定位置的开口。 在该方法中，使用与用作对准标记的第一开口对准的光掩模，在第一膜中形成第三开口。 第三开口被构造为用于将杂质引入半导体层的第二预定位置的开口。