公开(公告)号：US20230070355A1

公开(公告)日：2023-03-09

申请号：US17670912

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Changhyun KIM ,  Kyung-Eun BYUN

IPC: H01L29/49 ,  H01L29/40 ,  H01L21/28

Abstract: Disclosed are a layer structure including a metal layer and a carbon layer, a manufacturing method the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure according to an embodiment includes an insulating layer on one surface of a semiconductor layer, a first metal layer facing the semiconductor layer with the insulating layer therebetween, a conductive first carbon layer arranged between the insulating layer and the first metal layer, the conductive first carbon layer being in contact with a first surface of the first metal layer. The first metal layer may be provided above or below the semiconductor layer. The first carbon layer may include a graphene layer. The first carbon layer may extend to another surface of the first metal layer.

公开(公告)号：US20220415825A1

公开(公告)日：2022-12-29

申请号：US17549026

申请日：2021-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Junghoo SHIN ,  Kyung-Eun BYUN ,  Hyeonjin SHIN

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a conductive wiring having a certain pattern, a dielectric layer on side surfaces of the conductive wiring, a capping layer on the conductive wiring, and a graphene layer on the dielectric layer. The graphene layer may include a graphene material. A ratio of carbons having sp3 bonds to carbons having sp2 bonds in the graphene material is 1 or less.

公开(公告)号：US20210163296A1

公开(公告)日：2021-06-03

申请号：US17060893

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Changhyun KIM ,  Changseok LEE ,  Yeonchoo CHO

IPC: C01B32/186

Abstract: A method of forming graphene includes: preparing a substrate in a reaction chamber; performing a first growth process of growing a plurality of graphene aggregates apart from each other on the substrate at a first growth rate by using a reaction gas including a carbon source; and performing a second growth process of forming a graphene layer by growing the plurality of graphene aggregates at a second growth rate slower than the first growth rate by using the reaction gas including the carbon source.

公开(公告)号：US20210074815A1

公开(公告)日：2021-03-11

申请号：US17087968

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Seunggeol NAM ,  Seongjun PARK ,  Yunseong LEE

IPC: H01L29/16 ,  H01L21/02 ,  C01B32/186

Abstract: Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.

公开(公告)号：US20200350252A1

公开(公告)日：2020-11-05

申请号：US16861891

申请日：2020-04-29

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Keunwook SHIN ,  Kibum KIM ,  Hyunmi KIM ,  Hyeonjin SHIN ,  Sanghun LEE

IPC: H01L23/538 ,  H01L29/16 ,  H01L23/00 ,  H01L23/532

Abstract: An interconnect structure may include a graphene-metal barrier on a substrate and a conductive layer on the graphene-metal barrier. The graphene-metal barrier may include a plurality of graphene layers and metal particles on grain boundaries of each graphene layer between the plurality of graphene layers. The metal particles may be formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.

公开(公告)号：US20200294928A1

公开(公告)日：2020-09-17

申请号：US16884590

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun BYUN ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20200286732A1

公开(公告)日：2020-09-10

申请号：US16807702

申请日：2020-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Janghee LEE ,  Seunggeol NAM ,  Hyeonjin SHIN ,  Hyunseok LIM ,  Alum JUNG ,  Kyung-Eun BYUN ,  Jeonil LEE ,  Yeonchoo CHO

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/26

Abstract: Provided are a method of pre-treating a substrate and a method of directly forming graphene by using the method of pre-treating the substrate. In the method of pre-treating the substrate in the method of directly forming graphene, according to an embodiment, the substrate is pre-treated by using a pre-treatment gas including at least a carbon source and hydrogen. The method of directly forming graphene includes a process of pre-treating a substrate and a process of directly growing graphene on the substrate that is pre-treated. The process of pre-treating the substrate is performed according to the method of pre-treating the substrate.

公开(公告)号：US20240021679A1

公开(公告)日：2024-01-18

申请号：US18350433

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Junyoung KWON ,  Keunwook SHIN ,  Minseok YOO

IPC: H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/775

CPC classification number: H01L29/24 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/7853 ,  H01L29/775 ,  H01L29/04

Abstract: A semiconductor device may include a two-dimensional material layer including a two-dimensional semiconductor material having a polycrystalline structure; metallic nanoparticles partially on the two-dimensional material layer; a source electrode and a drain electrode respectively on both sides of the two-dimensional material layer; and a gate insulating layer and a gate electrode on the two-dimensional material layer between the source electrode and the drain electrode.

公开(公告)号：US20230157022A1

公开(公告)日：2023-05-18

申请号：US17986371

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Changhyun KIM ,  Sehun PARK ,  Hyunwoo KIM ,  Kyung-Eun BYUN ,  Dongjin YUN ,  Changseok LEE

IPC: H01L27/11582 ,  G06N3/063

CPC classification number: H01L27/11582 ,  G06N3/0635

Abstract: A vertical nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers each extending in a second direction crossing the first direction, the plurality of gate electrodes and the plurality of spacers being alternately arranged with each other in the first direction; and a gate insulating layer extending in the first direction between the channel layer and the plurality of gate electrodes. Each of the plurality of gate electrodes may include a metal-doped graphene.

公开(公告)号：US20230130702A1

公开(公告)日：2023-04-27

申请号：US17959812

申请日：2022-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sungtae KIM ,  Alum JUNG

IPC: H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a first dielectric layer including a trench, a conductive wire filling an inside of trench, and a cap layer on a top surface of the conductive wire. The cap layer may include graphene doped with a group V element. A second dielectric layer may be on a top surface of the first cap layer.