公开(公告)号：US20180191481A1

公开(公告)日：2018-07-05

申请号：US15901093

申请日：2018-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Hanmei Choi ,  Kihyun Hwang

IPC: H04L5/00 ,  H04L1/18

CPC classification number: H04L5/0091 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926 ,  H04L1/1812

Abstract: A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

公开(公告)号：USRE46389E1

公开(公告)日：2017-05-02

申请号：US14686984

申请日：2015-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

IPC: H01L21/8247 ,  H01L21/28

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

公开(公告)号：US20150041882A1

公开(公告)日：2015-02-12

申请号：US14493849

申请日：2014-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyul Lee ,  Bumsu Kim ,  Kwangmin Park ,  Hyun Park ,  Jae-young Ahn ,  Dongchul Yoo ,  Jongsik Chun ,  Kihyun Hwang

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

Abstract translation: 三维（3D）半导体存储器件包括电极分离图案，堆叠结构，数据存储层和沟道结构。 电极分离图案设置在基板上。 堆叠结构设置在电极分离图案的侧壁上。 堆叠结构包括与电极分离图案的侧壁相对的波纹状侧壁。 电极分离图案的侧壁垂直于基板。 数据存储层设置在波纹侧壁上。 通道结构设置在电荷存储层上。

公开(公告)号：US20140099761A1

公开(公告)日：2014-04-10

申请号：US14061304

申请日：2013-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract translation: 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US11723285B2

公开(公告)日：2023-08-08

申请号：US17655589

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Ahn ,  Oik Kwon ,  Jeonghee Park ,  Kihyun Hwang

IPC: H10N50/10 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/85 ,  H10N70/00

CPC classification number: H10N50/10 ,  H10B61/00 ,  H10B63/80 ,  H10N50/01 ,  H10N50/85 ,  H10N70/063 ,  H10N70/068 ,  H10N70/841 ,  H10N70/882

Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

公开(公告)号：US20220209103A1

公开(公告)日：2022-06-30

申请号：US17655589

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHOON AHN ,  Oik Kwon ,  Jeonghee Park ,  Kihyun Hwang

IPC: H01L43/08 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12 ,  H01L43/10

Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

公开(公告)号：US11057183B2

公开(公告)日：2021-07-06

申请号：US15901093

申请日：2018-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Hanmei Choi ,  Kihyun Hwang

IPC: H04L5/00 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H04L1/18

Abstract: A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

公开(公告)号：US10999045B2

公开(公告)日：2021-05-04

申请号：US15901093

申请日：2018-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Hanmei Choi ,  Kihyun Hwang

IPC: H04L5/00 ,  H01L29/78 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H04L1/18

Abstract: A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

公开(公告)号：US20180261626A1

公开(公告)日：2018-09-13

申请号：US15975861

申请日：2018-05-10

Applicant: Samsung Electronics Co. Ltd.

Inventor： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul yoo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/24 ,  H01L27/11556 ,  H01L45/00

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

公开(公告)号：US20140357054A1

公开(公告)日：2014-12-04

申请号：US14458998

申请日：2014-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Sung-Min Hwang ,  Kihyun Hwang ,  Jaehoon Jang

IPC: H01L21/762 ,  H01L27/115

CPC classification number: H01L21/76254 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42348

Abstract: A semiconductor device can include a first substrate and conductive patterns on the first substrate, where the conductive patterns are disposed in stacks vertically extending from the substrate. An active pillar can be on the first substrate vertically extend from the first substrate throughthe conductive patterns to provide vertical string transistors on the first substrate. A second substrate can be on the conductive patterns and the active pillar opposite the first substrate. A peripheral circuit transistor can be on the second substrate opposite the first substrate, where the peripheral circuit transistor can be adjacent to and overlap an uppermost pattern of the conductive patterns.

Abstract translation: 半导体器件可以包括第一衬底和第一衬底上的导电图案，其中导电图案布置在从衬底垂直延伸的堆叠中。 活性柱可以在第一衬底上，从第一衬底垂直地延伸穿过导电图案，以在第一衬底上提供垂直串联晶体管。 第二基板可以位于与第一基板相对的导电图案和有源柱上。 外围电路晶体管可以在与第一衬底相对的第二衬底上，其中外围电路晶体管可以与导电图案的最上面的图案相邻并且与其重叠。