公开(公告)号：US20220028859A1

公开(公告)日：2022-01-27

申请号：US17191308

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho HONG ,  Kyunghwan Lee ,  Hyuncheol Kim ,  Huijung Kim ,  Hyunmog Park ,  Kiseok Lee ,  Minhee Cho

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/24

Abstract: A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.

公开(公告)号：US20190319039A1

公开(公告)日：2019-10-17

申请号：US16454914

申请日：2019-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsoo Kim ,  Hyunmog Park ,  Joongshik Shin

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11575 ,  H01L27/06 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11563 ,  H01L21/822 ,  H01L27/1157

Abstract: A vertical memory device structure can include a vertical channel structure that vertically penetrates through an upper structure and a lower structure of a stack structure in a cell array region of the device. The vertical channel structure can have a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the lower structure. A vertical dummy structure can vertically penetrate through a staircase structure that is defined by the upper structure and the lower structure in a connection region of the device, and the vertical dummy structure can have a side wall with a planar profile at the level where the upper structure meets the lower structure.

公开(公告)号：US20180240811A1

公开(公告)日：2018-08-23

申请号：US15841644

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsoo Kim ,  Hyunmog Park ,  Joongshik Shin

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11578 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11563 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7926

Abstract: A vertical memory device structure can include a vertical channel structure that vertically penetrates through an upper structure and a lower structure of a stack structure in a cell array region of the device. The vertical channel structure can have a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the lower structure. A vertical dummy structure can vertically penetrate through a staircase structure that is defined by the upper structure and the lower structure in a connection region of the device, and the vertical dummy structure can have a side wall with a planar profile at the level where the upper structure meets the lower structure.

公开(公告)号：US12166132B2

公开(公告)日：2024-12-10

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Mintae Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Hyunmog Park ,  Kiseok Lee

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

公开(公告)号：US12119336B2

公开(公告)日：2024-10-15

申请号：US17883682

申请日：2022-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmog Park ,  Daehyun Kim ,  Jinmin Kim ,  Hei Seung Kim ,  Hyunsik Park ,  Sangkil Lee

IPC: H01L25/18 ,  G11C14/00 ,  G11C16/04 ,  H01L23/48 ,  H01L23/522 ,  H01L25/00 ,  H10B41/00 ,  H10B41/27 ,  H10B43/27 ,  G11C13/00 ,  H10B41/41

CPC classification number: H01L25/18 ,  G11C14/0018 ,  G11C16/04 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  G11C13/0004 ,  H10B41/41

Abstract: Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

公开(公告)号：US20240107775A1

公开(公告)日：2024-03-28

申请号：US18368098

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook Choi ,  Hyunmog Park ,  JIHONG KIM

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: An integrated circuit device includes a plurality of conductive lines on a semiconductor substrate, the plurality of conductive lines extending in a horizontal direction and overlapping each other in a vertical direction, a plurality of insulating layers alternating with the plurality of conductive lines in a vertical direction and extending in the horizontal direction, and a channel structure extending through the plurality of conductive lines and the plurality of insulating layers in the vertical direction. The channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, an information storage layer on an outside wall of the channel layer, and a pad pattern covering a top surface of the core insulating layer. The pad pattern contacts a portion of the outside wall of the channel layer and a topmost surface of the information storage layer.

公开(公告)号：US11922984B2

公开(公告)日：2024-03-05

申请号：US17949305

申请日：2022-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Woobin Song ,  Hyunmog Park ,  Sangkil Lee

IPC: G11C16/04 ,  G11C11/00 ,  G11C11/22 ,  G11C11/4096 ,  H10B12/00 ,  H10B51/30 ,  H10B51/40

CPC classification number: G11C11/005 ,  G11C11/223 ,  G11C11/2275 ,  G11C11/4096 ,  H10B12/33 ,  H10B12/50 ,  H10B51/30 ,  H10B51/40

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US20240015978A1

公开(公告)日：2024-01-11

申请号：US18320816

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siyeon Cho ,  Taeyoung Kim ,  Hyunmog Park ,  Bongyong Lee ,  Yukio Hayakawa

IPC: H10B51/20 ,  H10B51/10 ,  H01L23/528

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L23/5283

Abstract: Disclosed are semiconductor memory devices and electronic systems including the same. The semiconductor memory device may include a vertical channel perpendicular to a top surface of a substrate, word lines disposed on a first side of the vertical channel and vertically stacked on the substrate, back-gate electrodes disposed on a second side of the vertical channel and vertically stacked on the substrate, a ferroelectric layer disposed between the word lines and the first side of the vertical channel, a first intermediate insulating layer disposed between the ferroelectric layer and the first side of the vertical channel, and a second intermediate insulating layer disposed between the back-gate electrodes and the second side of the vertical channel.

公开(公告)号：US20220384661A1

公开(公告)日：2022-12-01

申请号：US17578893

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Kiseok Lee ,  Wonsok Lee ,  Mintae Ryu ,  Hyunmog Park ,  Woobin Song ,  Sungwon Yoo

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes: a conductive line that extends in a first direction on a substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction, the trench having an extension portion that extends into the conductive line; a channel layer on opposite sidewalls of the trench and connected to a region, exposed by the trench, of the conductive line; first and second gate electrodes on the channel layer, and respectively along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact, respectively buried in the insulating pattern layer, and respectively connected to upper regions of the channel layer.

公开(公告)号：US11018137B2

公开(公告)日：2021-05-25

申请号：US16442769

申请日：2019-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/10 ,  G11C11/40 ,  H01L27/108 ,  G11C11/402

Abstract: A semiconductor memory device includes a substrate, a first active pattern on the substrate, a gate electrode intersecting a channel region of the first active pattern, a first insulating layer covering the first active pattern and the gate electrode, a contact penetrating the first insulating layer so as to be electrically connected to a first source/drain region of the first active pattern, and a second active pattern on the first insulating layer. A channel region of the second active pattern vertically overlaps with the contact.