公开(公告)号：US09984760B1

公开(公告)日：2018-05-29

申请号：US15403710

申请日：2017-01-11

Applicant: SanDisk Technologies LLC

Inventor： Zhengyi Zhang ,  Liang Pang ,  Yingda Dong

IPC: G11C16/28 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/3431 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/28 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel of the string is charged up from a source end of the string. However, there is a delay in charging up a drain end of the channel. A voltage detector connected to a bit line detects when a drain end of the channel reaches a reference voltage. When the reference voltage is reached, a voltage of the select gate transistor at the drain end of the string can be floated. This avoids unintentional programming of the select gate transistor which could otherwise occur if the voltage was floated to soon. Also, a substrate voltage may be ramped up to a first detected level before being ramped up to a second, final level.

公开(公告)号：US20180114580A1

公开(公告)日：2018-04-26

申请号：US15440185

申请日：2017-02-23

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/563

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die.

公开(公告)号：US09941293B1

公开(公告)日：2018-04-10

申请号：US15291871

申请日：2016-10-12

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Jayavel Pachamuthu ,  Yingda Dong

IPC: H01L29/788 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11519 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833

Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

公开(公告)号：US09793283B1

公开(公告)日：2017-10-17

申请号：US15278988

申请日：2016-09-28

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Jayavel Pachamuthu ,  Yingda Dong

IPC: H01L29/788 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/16 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L27/11556 ,  H01L21/02381 ,  H01L21/02532 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/0657 ,  H01L29/16

Abstract: Disclosed herein is a 3D memory with vertical NAND strings, and method for fabricating the same. Each vertical NAND string has a source side select transistor having a body in contact with a single crystal silicon substrate. The NAND string channel is formed from silicon germanium (SiGe), which provides for greater electron mobility than silicon. The body of the source side select transistor comprises epitaxial crystalline silicon germanium (SiGe) in contact with the single crystal silicon substrate. By epitaxial crystalline SiGe it is meant that the crystalline SiGe has the same crystalline orientation as the single crystal silicon substrate.

公开(公告)号：US10394649B2

公开(公告)日：2019-08-27

申请号：US15921184

申请日：2018-03-14

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G11C29/04 ,  G06F11/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G11C11/56 ,  G11C16/32

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

公开(公告)号：US10128257B2

公开(公告)日：2018-11-13

申请号：US15906317

申请日：2018-02-27

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Jayavel Pachamuthu ,  Yingda Dong

IPC: H01L27/115 ,  H01L27/11519 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66 ,  H01L27/1158 ,  H01L27/11553

Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

公开(公告)号：US20180308556A1

公开(公告)日：2018-10-25

申请号：US15495178

申请日：2017-04-24

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yingda Dong ,  Ching-Huang Lu ,  Nan Lu ,  Hong-Yan Chen

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3459

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

公开(公告)号：US20180233206A1

公开(公告)日：2018-08-16

申请号：US15430299

申请日：2017-02-10

Applicant: SanDisk Technologies LLC

Inventor： Xuehong Yu ,  Liang Pang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3431 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/44 ,  G11C2029/1202

Abstract: A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.

公开(公告)号：US09952944B1

公开(公告)日：2018-04-24

申请号：US15333440

申请日：2016-10-25

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G11C16/10 ,  G06F11/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C29/52 ,  G11C2207/2281

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

公开(公告)号：US20180102375A1

公开(公告)日：2018-04-12

申请号：US15291871

申请日：2016-10-12

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Jayavel Pachamuthu ,  Yingda Dong

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/11519 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833

Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.