公开(公告)号：US20230164990A1

公开(公告)日：2023-05-25

申请号：US17673137

申请日：2022-02-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/15

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/151

Abstract: A three-dimensional memory device containing a plurality of levels of memory elements includes a memory film containing a layer stack that includes a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer, a semiconductor channel, and a control gate electrode.

公开(公告)号：US20220013518A1

公开(公告)日：2022-01-13

申请号：US17411635

申请日：2021-08-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho KIM ,  Masaaki HIGASHITANI ,  Fumiaki TOYAMA ,  Akio NISHIDA

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/00 ,  H01L27/11575 ,  H01L27/1157

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

公开(公告)号：US20210351058A1

公开(公告)日：2021-11-11

申请号：US16867818

申请日：2020-05-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shoichi MURAKAMI ,  Shigeru NAKATSUKA ,  Syo FUKATA ,  Yusuke OSAWA ,  Shigehiro FUJINO ,  Masaaki HIGASHITANI

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/687 ,  H01J37/32

Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.

公开(公告)号：US20210348272A1

公开(公告)日：2021-11-11

申请号：US16868787

申请日：2020-05-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shoichi MURAKAMI ,  Shigeru NAKATSUKA ,  Syo FUKATA ,  Yusuke OSAWA ,  Shigehiro FUJINO ,  Masaaki HIGASHITANI

IPC: C23C16/458 ,  H01L21/02 ,  H01L21/683 ,  H01L21/687 ,  H01J37/32 ,  H01L21/033 ,  C23C16/50 ,  C23C16/455

Abstract: A deposition chamber includes a vacuum enclosure, an electrostatic chuck having a flat top surface located within a vacuum enclosure, a lift-and-rotation unit extending through or laterally surrounding the electrostatic chuck at a position that is laterally offset from a vertical axis passing through a geometrical center of the electrostatic chuck, a gas supply manifold configured to provide influx of gas into the vacuum enclosure, and a pumping port connected to the vacuum enclosure.

公开(公告)号：US20210327838A1

公开(公告)日：2021-10-21

申请号：US17357120

申请日：2021-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Masaaki HIGASHITANI ,  Ramy Nashed Bassely SAID

IPC: H01L23/00

Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.

公开(公告)号：US20210264959A1

公开(公告)日：2021-08-26

申请号：US16798686

申请日：2020-02-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: G11C11/22 ,  H01L27/1159 ,  H01L29/778 ,  H01L29/16

Abstract: A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.

公开(公告)号：US20210091204A1

公开(公告)日：2021-03-25

申请号：US16577176

申请日：2019-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L29/51 ,  H01L29/417 ,  H01L21/28 ,  H01L27/11514

Abstract: A semiconductor structure contains a semiconductor channel extending between a source region and a drain region, at least one gate electrode, a ferroelectric material portion located between the semiconductor channel and the at least one gate electrode, a front-side gate dielectric located between the ferroelectric material portion and the semiconductor channel, and a backside gate dielectric located between the ferroelectric material portion and the at least one gate electrode. The front-side gate dielectric and the backside gate dielectric have a dielectric constant greater than 7.9 and a band gap greater than a band gap of the ferroelectric material portion.

公开(公告)号：US20240127864A1

公开(公告)日：2024-04-18

申请号：US18350573

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  James KAI ,  Johann ALSMEIER

IPC: G11C5/06 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C5/063 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device includes a first memory block containing first word lines and a first source layer segment, and a second memory block containing second word lines and a second source layer segment which is electrically isolated from the first source layer segment. The first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block.

公开(公告)号：US20230363161A1

公开(公告)日：2023-11-09

申请号：US18045070

申请日：2022-10-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical composite metal oxide semiconductor channel that contains an outer semiconducting metal oxide channel layer having a first band gap and an inner semiconducting metal oxide channel layer having a second band gap that is different from the first band gap.

公开(公告)号：US20230363158A1

公开(公告)日：2023-11-09

申请号：US17661783

申请日：2022-05-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical composite metal oxide semiconductor channel having a different composition between its inner and outer portions.