公开(公告)号：US20220404989A1

公开(公告)日：2022-12-22

申请号：US17349306

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G06F3/06

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

公开(公告)号：US20210142858A1

公开(公告)日：2021-05-13

申请号：US16681968

申请日：2019-11-13

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Naoki Ookuma ,  Toru Miwa

IPC: G11C16/28 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/04

Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.

公开(公告)号：US20200185397A1

公开(公告)日：2020-06-11

申请号：US16213180

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: H01L27/11548 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US20170263642A1

公开(公告)日：2017-09-14

申请号：US15607837

申请日：2017-05-30

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Kota Funayama ,  Toru Miwa ,  Hiroyuki Ogawa

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L28/20

Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.

公开(公告)号：US20240233826A1

公开(公告)日：2024-07-11

申请号：US18357339

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Toru Miwa

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/3459

Abstract: A non-volatile memory system is configured to program non-volatile memory cells by applying doses of programming to the memory cells and performing a program-verify operation following each dose of programming. Each dose of programming and the corresponding program-verify operation following the dose of programming is referred to as a program loop. The program-verify operation comprises applying a verify reference voltage to a selected word line and applying an overdrive voltage to unselected word lines. To reduce the amount of current used, the memory system includes a loop dependent reduction in the ramp-up rate of the overdrive voltage applied to unselected word lines during program-verify.

公开(公告)号：US20240128132A1

公开(公告)日：2024-04-18

申请号：US18221803

申请日：2023-07-13

Applicant: SanDisk Technologies LLC

Inventor： Toru Miwa ,  Takashi Murai ,  Hiroyuki Ogawa ,  Nisha Padattil Kuliyampattil

IPC: H01L21/66 ,  G01R1/073 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R1/07342 ,  H01L24/05 ,  H01L24/06 ,  H01L25/0657

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

公开(公告)号：US11875043B1

公开(公告)日：2024-01-16

申请号：US17943560

申请日：2022-09-13

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Toru Miwa

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

Abstract: To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels following a programming pulse, differing amounts of wait time are used before biasing a selected word line to the verify levels or levels. For example, if only a single verify level is used, a shorter delay is used than if two verify levels are used.

公开(公告)号：US20220406398A1

公开(公告)日：2022-12-22

申请号：US17349321

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G11C29/00 ,  G11C29/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

公开(公告)号：US11177277B2

公开(公告)日：2021-11-16

申请号：US16675800

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Naoki Ookuma ,  Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Toru Miwa

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/027

Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.

公开(公告)号：US11081192B2

公开(公告)日：2021-08-03

申请号：US16668949

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Yuki Fujita ,  Naoki Ookuma ,  Kazuki Yamauchi ,  Masahito Takehara ,  Toru Miwa

IPC: G11C16/32 ,  G11C16/26

Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.