公开(公告)号：US20150236172A1

公开(公告)日：2015-08-20

申请号：US14181207

申请日：2014-02-14

Applicant: Semiconductor Components Industries, LLC

Inventor： Mohammed Tanvir Quddus ,  Mihir Mudholkar ,  Mark Griswold ,  Ali Salih

IPC: H01L29/872 ,  H01L29/66

CPC classification number: H01L29/47 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/28537 ,  H01L29/0615 ,  H01L29/66143 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/872 ,  H01L29/8725

Abstract: A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.

Abstract translation: 肖特基器件包括在半导体材料的一部分中的势垒高度调节层。 根据一个实施例，肖特基器件由第一导电类型的半导体材料形成，该半导体材料具有从半导体材料的第一主表面延伸到半导体材料中的第二导电类型的势垒高度调节层， 小于零偏置耗尽边界。 形成与掺杂层接触的肖特基接触。

公开(公告)号：US10741682B2

公开(公告)日：2020-08-11

申请号：US15807237

申请日：2017-11-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Ali Salih ,  Llewellyn Vaughan-Edmunds

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/08 ,  H01L29/872 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

Abstract: High-electron-mobility transistor (HEMT) devices are described in this patent application. In some implementations, the HEMT devices can include a back barrier hole injection structure. In some implementations, the HEMT devices include a conductive striped portion electrically coupled to a drain contact.

公开(公告)号：US20200066568A1

公开(公告)日：2020-02-27

申请号：US16664758

申请日：2019-10-25

Applicant: Semiconductor Components Industries, LLC

Inventor： Ali Salih ,  Gordon M. Grivna

IPC: H01L21/683 ,  H01L29/778 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/306 ,  H01L21/304 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/78 ,  H01L27/06

Abstract: An electronic device can include a semiconductor material and a semiconductor layer overlying the semiconductor material, wherein the semiconductor layer has a greater bandgap energy as compared to the semiconductor material. The electronic device can include a component having a high electrical field region and a low electrical field region. Within the high electrical field region, the semiconductor material is not present. In another embodiment, the component may not be present. In another aspect, a process can include providing a substrate and a semiconductor layer overlying the substrate; removing a first portion of the substrate to define a first trench; forming a first insulating layer within the first trench; removing a second portion of the substrate adjacent to first insulating layer to define second trench; and forming a second insulating layer within the second trench.

公开(公告)号：US10276713B2

公开(公告)日：2019-04-30

申请号：US15487517

申请日：2017-04-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Balaji Padmanabhan ,  Ali Salih ,  Peter Moens

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/10 ,  H01L29/778 ,  H01L21/74 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762 ,  H01L29/417 ,  H01L21/76 ,  H01L21/763 ,  H01L21/02

Abstract: In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

公开(公告)号：US09960234B2

公开(公告)日：2018-05-01

申请号：US14508266

申请日：2014-10-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kirk Huang ,  Chun-Li Liu ,  Ali Salih

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/20 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L29/0696 ,  H01L27/0629 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/78

Abstract: In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value.

公开(公告)号：US09773693B2

公开(公告)日：2017-09-26

申请号：US15047874

申请日：2016-02-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. Grivna ,  Zia Hossain ,  Ali Salih

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/768 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/76205 ,  H01L21/76816 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.

公开(公告)号：US09620443B2

公开(公告)日：2017-04-11

申请号：US15208703

申请日：2016-07-13

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Ali Salih ,  Chun-Li Liu ,  Phillip Celaya

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/4825 ,  H01L21/4882 ,  H01L23/3735 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

公开(公告)号：US20170025339A1

公开(公告)日：2017-01-26

申请号：US15207626

申请日：2016-07-12

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/37099 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49112 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1306 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

Abstract translation: 半导体部件包括具有与其一体形成的引线的支撑件。 绝缘金属基板安装在支撑体的表面上，半导体芯片安装在绝缘金属基板上。 基于III-N的半导体芯片安装到绝缘金属基板上，其中III-N基半导体芯片具有栅极焊盘，漏极接合焊盘和源极焊盘。 硅基半导体芯片安装在基于III-N的半导体芯片上。 根据实施例，硅基半导体芯片包括具有栅极接合焊盘，漏极接合焊盘和源极焊盘的器件。 III-N型半导体芯片的漏极接合焊盘可以结合到衬底或引线上。 根据另一个实施例，硅基半导体芯片是二极管。

公开(公告)号：US20170025338A1

公开(公告)日：2017-01-26

申请号：US15204604

申请日：2016-07-07

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Ali Salih ,  Chun-Li Liu

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/49575 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/40 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.

Abstract translation: 根据实施例，半导体部件包括具有第一和第二器件接收结构的支撑件。 由III-N半导体材料配置的半导体器件耦合到支撑件，其中半导体器件具有相对的表面。 第一接合焊盘从第一表面的第一部分延伸，第二接合焊盘从第一表面的第二部分延伸，并且第三接合焊盘从第一表面的第三部分延伸。 第一接合焊盘耦合到第一器件接收部分，漏极接合焊盘耦合到第二器件接收部分，并且第三接合焊盘耦合到第三引线。 根据另一实施例，一种方法包括将包括III-N半导体衬底材料的半导体芯片耦合到支撑体。

公开(公告)号：US20170025337A1

公开(公告)日：2017-01-26

申请号：US15204261

申请日：2016-07-07

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  Ali Salih ,  Prasad Venkatraman

IPC: H01L23/495 ,  H01L29/772 ,  H01L29/20 ,  H01L21/48 ,  H01L29/861

CPC classification number: H01L23/49575 ,  H01L21/4853 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L29/2003 ,  H01L29/772 ,  H01L2224/0603 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2224/37099 ,  H01L2224/45099

Abstract: In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer.

Abstract translation: 根据实施例，半导体部件包括支撑件和多个引线。 绝缘金属基板，具有第一部分和第二部分结合到支撑体上。 包含III-N半导体材料的半导体芯片被接合到绝缘金属基板的第一部分，并且第一电互连件耦合在绝缘金属基板的第一部分的漏极接合焊盘之间。 第二半导体芯片被结合到第一电互连。 耦合在所述多个引线的引线和所述第二半导体芯片之间的第二电互连。 根据另一实施例，制造半导体部件的方法包括将第一半导体芯片耦合到第一导电层并将第二半导体芯片耦合到第二导电层。