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    ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
    25.
    发明申请
    ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20230111192A1

    公开(公告)日：2023-04-13

    申请号：US17527434

    申请日：2021-11-16

    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

    Inventor： Yi-Min Fu ,  Chi-Ching Ho ,  Cheng-Yu Kang ,  Yu-Po Wang

    IPC: H01L23/498 ,  H01L23/367 ,  H01L21/48

    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.

    Packaging substrate and fabrication method thereof
    27.
    发明授权
    Packaging substrate and fabrication method thereof 有权
    包装基板及其制造方法

    公开(公告)号：US09265154B2

    公开(公告)日：2016-02-16

    申请号：US14461828

    申请日：2014-08-18

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Shao-Tzu Tang ,  Chi-Ching Ho ,  Ying-Chou Tsai

    IPC: H01L21/8242 ,  H05K1/18 ,  H05K1/11 ,  H05K3/10 ,  H01L49/02

    CPC classification number: H05K1/186 ,  H01L23/49822 ,  H01L23/50 ,  H01L28/40 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/10 ,  H05K3/42 ,  H05K2201/10015 ,  H05K2203/0733 ,  H01L2924/00

    Abstract: A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.

    Abstract translation: 提供一种封装基板的制造方法，其包括以下步骤：在载体上形成第一导电部分; 在每个第一导电部分上依次形成导电柱和取向层; 在载体上形成密封剂，用于封装第一导电部分，导电柱和对准层; 在所述密封剂中的每个取向层上形成导电孔，并在所述导电通孔和所述密封剂上形成第二导电部分; 并移除载体。 每个第一导电部分和相应的导电柱，对准层和导电通孔形成导电结构。 取向层具有大于导电柱和导电通孔的垂直投影面积，从而减小导电柱和导电通孔的尺寸，从而增加布线密度和电子元件安装密度。

    Packaging substrate and semiconductor package
    28.
    发明授权
    Packaging substrate and semiconductor package 有权
    封装基板和半导体封装

    公开(公告)号：US08810045B2

    公开(公告)日：2014-08-19

    申请号：US13644561

    申请日：2012-10-04

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Chi-Ching Ho ,  Yu-Chih Yu ,  Ying-Chou Tsai

    IPC: H01L23/28

    CPC classification number: H01L21/48 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/83 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

    Abstract: A packaging substrate and a semiconductor package each include: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer.

    Abstract translation: 封装基板和半导体封装均包括：具有第一表面和与第一表面相对的第二表面的金属板，其中第一表面具有多个用于在其间限定第一芯电路层的第一开口，第二表面具有 用于在其间限定第二芯电路层的多个第二开口，所述第一开口和所述第二开口中的每一个具有宽的外部部分和窄的内部部分，并且每个所述第二开口的内部部分与所述第二开口的内部部分连通 第一开口中的对应的一个; 形成在第一开口中的第一密封剂; 形成在第二开口中的第二密封剂; 以及形成在第一密封剂和第一芯电路层上的表面电路层。

    PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
    29.
    发明申请
    PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 有权
    包装基板，半导体封装及其制造方法

    公开(公告)号：US20130334694A1

    公开(公告)日：2013-12-19

    申请号：US13644561

    申请日：2012-10-04

    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

    Inventor： Chi-Ching Ho ,  Yu-Chih Yu ,  Ying-Chou Tsai

    IPC: H05K1/02 ,  B05D3/00 ,  B05D5/12 ,  H01L23/14 ,  H01L21/56

    CPC classification number: H01L21/48 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/83 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

    Abstract: A packaging substrate is provided, including: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer. The present invention effectively reduces the fabrication cost and increases the product reliability.

    Abstract translation: 提供了一种包装衬底，包括：具有第一表面和与第一表面相对的第二表面的金属板，其中第一表面具有多个用于在其间限定第一芯电路层的第一开口，第二表面具有多个 的用于在其间限定第二芯电路层的第二开口，第一和第二开口中的每一个具有宽的外部部分和窄的内部部分，并且每个第二开口的内部部分与相应的第二开口的内部部分连通 第一个开口之一; 形成在第一开口中的第一密封剂; 形成在第二开口中的第二密封剂; 以及形成在所述第一密封剂和所述第一芯电路层上的表面电路层。 本发明有效地降低了制造成本，提高了产品的可靠性。

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