公开(公告)号：US20180090835A1

公开(公告)日：2018-03-29

申请号：US15596113

申请日：2017-05-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Yuan Shih ,  Chih-Hsien Chiu ,  Yueh-Chiung Chang ,  Tsung-Li Lin ,  Chi-Pin Tsai ,  Chien-Cheng Lin ,  Tsung-Hsien Tsai ,  Heng-Cheng Chu ,  Ming-Fan Tsai

IPC: H01Q1/52 ,  H01Q1/22 ,  H01Q1/48 ,  H01L23/552 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/66

CPC classification number: H01Q1/526 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2224/48091 ,  H01Q1/2283 ,  H01Q1/243 ,  H01Q1/48 ,  H01Q9/42 ,  H01L2924/00014

Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.

公开(公告)号：US20160225728A1

公开(公告)日：2016-08-04

申请号：US15094125

申请日：2016-04-08

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tsung-Hsien Tsai ,  Heng-Cheng Chu ,  Chien-Cheng Lin ,  Chih-Hsien Chiu ,  Hsin-Lung Chung ,  Yude Chu

IPC: H01L23/66 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/66 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/64 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L25/16 ,  H01L25/50 ,  H01L28/00 ,  H01L2223/6661 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括：具有多个导电焊盘的衬底和围绕形成在其表面上的导电焊盘的多个焊盘; 安装在导电焊盘上的多个无源器件; 绝缘层，其形成在所述表面上并且具有嵌入其中的无源器件的一部分; 安装在所述绝缘层的顶表面上的半导体芯片; 电连接半导体芯片和接合焊盘的多个接合线; 形成在基板的表面上以封装绝缘层，接合线和半导体芯片的密封剂，其中投射到基板上的半导体芯片的区域覆盖无源器件中最外面的一个的一部分。 因此，无源器件的安装密度提高。

公开(公告)号：US20150340248A1

公开(公告)日：2015-11-26

申请号：US14817624

申请日：2015-08-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tsung-Hsien Tsai ,  Chih-Hsien Chiu ,  Hsin-Lung Chung ,  Chien-Cheng Lin

IPC: H01L21/48 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.

Abstract translation: 具有ESD（静电放电）和EMI（电磁干扰）防止功能的封装包括：具有接地结构和设置在其中的I / O结构的衬底单元; 至少一个半导体部件，设置在所述基板单元的表面上并电连接到所述接地结构和所述I / O结构; 覆盖所述基板单元和所述半导体部件的表面的密封剂; 以及金属层，其设置在基板单元的密封剂和侧表面的暴露表面上并与基底结构电绝缘，从而保护半导体部件免受ESD和EMI，从而提高产品产量并降低短路的风险。

公开(公告)号：US20140203395A1

公开(公告)日：2014-07-24

申请号：US14087554

申请日：2013-11-22

Applicant: Siliconware Precision industries Co., Ltd

Inventor： Tsung-Hsien Tsai ,  Heng-Cheng Chu ,  Chien-Cheng Lin ,  Chih-Hsien Chiu ,  Hsin-Lung Chung ,  Yude Chu

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L23/66 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/64 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L25/16 ,  H01L25/50 ,  H01L28/00 ,  H01L2223/6661 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括：具有多个导电焊盘的衬底和围绕形成在其表面上的导电焊盘的多个焊盘; 安装在导电焊盘上的多个无源器件; 绝缘层，其形成在所述表面上并且具有嵌入其中的无源器件的一部分; 安装在所述绝缘层的顶表面上的半导体芯片; 电连接半导体芯片和接合焊盘的多个接合线; 形成在基板的表面上以封装绝缘层，接合线和半导体芯片的密封剂，其中投射到基板上的半导体芯片的区域覆盖无源器件中最外面的一个的一部分。 因此，无源器件的安装密度提高。