公开(公告)号：US20210098593A1

公开(公告)日：2021-04-01

申请号：US17119867

申请日：2020-12-11

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  C23C14/04 ,  C23C14/22

Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

公开(公告)号：US20200279954A1

公开(公告)日：2020-09-03

申请号：US16878287

申请日：2020-05-19

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01J21/10

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

公开(公告)号：US20190393358A1

公开(公告)日：2019-12-26

申请号：US16564860

申请日：2019-09-09

Applicant: STMicroelectronics, Inc.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/84 ,  H01H59/00 ,  H01H1/00 ,  B82B3/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US20160293739A1

公开(公告)日：2016-10-06

申请号：US15177231

申请日：2016-06-08

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

Abstract translation: 垂直隧道FET（TFET）为关键尺寸低于7nm的晶体管提供低功耗，高速开关性能。 垂直TFET使用全栅（GAA）器件结构，其具有在形成于硅衬底中的掺杂阱的表面上方延伸的圆柱形结构。 圆柱形结构包括从掺杂阱外延生长的下部漏极区域，沟道和上部源极区域。 该通道由本征硅制成，而源极和漏极区域原位掺杂。 环形栅极围绕通道，电容性地控制从所有侧面通过通道的电流。 源极可以通过前侧触点电接触，而漏极通过背面触点进行访问，该触点提供低接触电阻并且还用作散热器。 垂直TFET集成电路的可靠性通过将垂直TFET耦合到静电放电（ESD）二极管来增强。

公开(公告)号：US20160254343A1

公开(公告)日：2016-09-01

申请号：US15082987

申请日：2016-03-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. ZHANG

IPC: H01L49/02 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0676 ,  H01L27/0682 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

Abstract translation: 制造半导体器件的方法可以包括在半导体衬底上形成第一电介质层，在第一电介质层中形成第一沟槽，用导电材料填充第一沟槽，去除导电材料的上部以限定下部 导电构件，其上方具有凹部，在凹部中形成填充介电材料以限定第二沟槽。 该方法还可以包括用导电材料填充第二沟槽以限定上导电构件，在第一电介质层和上导电构件上形成第二电介质层，形成通过第二电介质层和下面的填充介电材料的第一通孔， 下导电构件，并且通过第二电介质层形成到上导电构件的第二通孔。

公开(公告)号：US20160190312A1

公开(公告)日：2016-06-30

申请号：US14588337

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John H. ZHANG ,  Carl RADENS ,  Lawrence A. CLEVENGER ,  Yiheng XU

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/28 ,  H01L29/267 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L29/7827 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66666

Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

Abstract translation: 公开了垂直GAA FET结构，其中载流纳米线基本上垂直于硅衬底的表面取向。 垂直GAA FET旨在满足7 nm技术生成的设计和性能标准。 在一些实施例中，可以经由衬底的背面制造垂直取向的GAA FET的漏极和栅极端子的电接触。 公开了各种n型和p型晶体管设计具有不同接触构造的实例。 在一个示例中，背面栅极触点延伸穿过相邻器件之间的隔离区域。 其他实施例具有用于电路设计灵活性的双栅极触点。 可以使用不同的接触配置来调整金属图案密度。

公开(公告)号：US20240145480A1

公开(公告)日：2024-05-02

申请号：US18326841

申请日：2023-05-31

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L27/12 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B20/00

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H10B10/12 ,  H10B10/125 ,  H10B20/27 ,  H01L2924/0002

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US20210343829A1

公开(公告)日：2021-11-04

申请号：US17373586

申请日：2021-07-12

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L49/02 ,  H01L27/108 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11507

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

公开(公告)号：US20180315701A1

公开(公告)日：2018-11-01

申请号：US15967336

申请日：2018-04-30

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L27/08 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0676 ,  H01L27/0682 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

公开(公告)号：US20180182902A1

公开(公告)日：2018-06-28

申请号：US15892028

申请日：2018-02-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/84 ,  H01H49/00 ,  B82B3/00 ,  H01H1/00 ,  H01H59/00 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.