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    Memory device and method for in-memory computing
    22.
    发明授权
    Memory device and method for in-memory computing 有权

    公开(公告)号：US11756615B2

    公开(公告)日：2023-09-12

    申请号：US17462250

    申请日：2021-08-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marcella Carissimi ,  Marco Pasotti ,  Roberto Antonio Canegallo

    IPC: G11C11/00 ,  G11C13/00 ,  G06N3/02

    CPC classification number: G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0004 ,  G11C13/0038 ,  G06N3/02

    Abstract: An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.

    Positive and negative charge pump control
    23.
    发明授权
    Positive and negative charge pump control 有权

    公开(公告)号：US11611275B2

    公开(公告)日：2023-03-21

    申请号：US17866372

    申请日：2022-07-15

    Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

    Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

    IPC: H02M3/07 ,  G11C5/14

    Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

    MEMORY DEVICE AND METHOD FOR IN-MEMORY COMPUTING
    24.
    发明申请
    MEMORY DEVICE AND METHOD FOR IN-MEMORY COMPUTING 有权

    公开(公告)号：US20220068380A1

    公开(公告)日：2022-03-03

    申请号：US17462250

    申请日：2021-08-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marcella Carissimi ,  Marco Pasotti ,  Roberto Canegallo

    IPC: G11C13/00

    Abstract: An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.

    Measuring leakage currents and measuring circuit for carrying out such measuring
    29.
    发明授权
    Measuring leakage currents and measuring circuit for carrying out such measuring 有权
    测量泄漏电流和进行这种测量的测量电路

    公开(公告)号：US09442149B2

    公开(公告)日：2016-09-13

    申请号：US14326263

    申请日：2014-07-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marco Pasotti ,  Fabio De Santis

    IPC: H01H31/12 ,  G01R31/02 ,  G01R19/165

    CPC classification number: G01R31/025 ,  G01R19/16571

    Abstract: An embodiment of a measuring circuit for measuring the leakage current flowing in a portion of an electronic device when said portion is biased by a biasing unit of the electronic device is proposed. The measuring circuit includes a first section configured to generate a threshold current, a second section configured to receive the leakage current, a third section configured to compare the threshold current with the leakage current, and a fourth section configured to generate an output voltage based on the comparison between the threshold current and the leakage current. Said first section is configured to set the value of said threshold current to a different value at each reiteration of an operating cycle. Said fourth section is configured to measure said leakage current based on a detection of a change in the value of the output voltage between two reiterations of the operating cycle.

    Abstract translation: 提出了一种测量电路的实施例，用于测量当电子设备的偏置单元偏压所述部分时在电子设备的一部分中流动的漏电流。 测量电路包括被配置为产生阈值电流的第一部分，被配置为接收泄漏电流的第二部分，被配置为将阈值电流与漏电流进行比较的第三部分，以及被配置为基于 阈值电流与漏电流的比较。 所述第一部分被配置为在操作周期的每次重复时将所述阈值电流的值设置为不同的值。 所述第四部分被配置为基于在操作周期的两次重复之间的输出电压的值的变化的检测来测量所述泄漏电流。

    Error correction in differential memory devices with reading in single-ended mode in addition to reading in differential mode
    30.
    发明授权
    Error correction in differential memory devices with reading in single-ended mode in addition to reading in differential mode 有权
    除了读差分模式之外，在单端模式下读差分存储器件进行纠错

    公开(公告)号：US09349490B2

    公开(公告)日：2016-05-24

    申请号：US14597824

    申请日：2015-01-15

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Marcella Carissimi ,  Marco Pasotti

    IPC: G11C29/00 ,  G11C29/52 ,  G11C7/18 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/28 ,  G06F11/10

    CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C7/18 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/4013

    Abstract: A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.

    Abstract translation: 差分存储器件包括具有直接存储单元和补充存储单元的存储单元。 相应的方法包括接收读取与所选码字相关联的所选数据字的请求，读取表示所选码字的差分版本的差分码字，根据纠错码验证差分码字，设置所选择的码字 数据字根据差分代码字响应积极的验证。 该方法还包括读取表示所选码字的单端版本的至少一个单端码字，根据纠错码验证单端码字，并根据单频码字单位设置所选择的数据字， 响应于对差分代码字的否定验证和对单端代码字的肯定验证，结束代码字。

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