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公开(公告)号：US10675881B2
公开(公告)日：2020-06-09
申请号：US16220476
申请日：2018-12-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista , Victorien Brecte
Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
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公开(公告)号：US10558609B2
公开(公告)日：2020-02-11
申请号：US16204660
申请日：2018-11-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Chama Ameziane El Hassani
Abstract: In an embodiment, an electronic device for filtering an incoming digital signal includes several elementary filtering modules that include an elementary input configured to receive an incident elementary signal extracted from an incoming signal, an elementary output, and a dedicated capacitive circuit. The device further includes a resistive circuit common to all the elementary filtering modules and configured for cooperating with the capacitive circuit of each elementary filtering module in such a manner as to filter, on the respective elementary output, pulses of the incident elementary signal having a first voltage level and a duration less than a time constant and to deliver a filtered elementary signal on the elementary output.
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公开(公告)号：US20190067307A1
公开(公告)日：2019-02-28
申请号：US16057193
申请日：2018-08-07
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
IPC: H01L27/11526 , G11C16/04 , G11C16/14 , G11C16/10
CPC classification number: H01L27/11526 , G11C5/025 , G11C16/0433 , G11C16/06 , G11C16/10 , G11C16/14 , H01L27/11524 , H01L27/11529
Abstract: A memory device includes a memory plane including a succession of neighboring semiconductor recesses of a first type of conductivity, wherein each semiconductor recess houses a plurality of memory words including a plurality of memory cells, wherein each memory cell includes a state transistor having a floating gate and a control gate. The memory device further includes a plurality of control gate selection transistors respectively allocated to each memory word of the plurality of memory words, wherein each control gate selection transistor is coupled to the control gates of the state transistors of the memory word to which the control gate selection transistor is allocated, wherein each control gate selection transistor is situated in and on a neighbor semiconductor recess of the semiconductor recess housing the memory word to which the control gate selection transistor is allocated.
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公开(公告)号：US10049753B2
公开(公告)日：2018-08-14
申请号：US15657492
申请日：2017-07-24
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Victorien Brecte
Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
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公开(公告)号：US20180033487A1
公开(公告)日：2018-02-01
申请号：US15436829
申请日：2017-02-19
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet
IPC: G11C16/04 , H01L27/11521 , H01L29/423 , H01L27/11556 , G11C16/14 , G11C16/12 , H01L27/11519 , H01L27/11526
CPC classification number: G11C16/0433 , G11C16/0425 , G11C16/12 , G11C16/14 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L29/42324 , H01L29/42344 , H01L29/7883
Abstract: A memory cell includes a source region and a drain region disposed in a semiconductor body. A channel region is disposed in the semiconductor body between the source region and the drain region. A floating gate is disposed between the semiconductor body and the control gate. The floating gate includes a protruding portion that is located over the channel region between the source and drain regions and spaced therefrom. The protruding portion is separated from the channel region by a first insulating layer that is thinner than a second insulating layer that separates remaining portions of the floating gate from the channel region.
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Patent Agency Ranking
公开(公告)号：US20170345502A1
公开(公告)日：2017-11-30
申请号：US15682102
申请日：2017-08-21
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet
IPC: G11C16/04 , H01L27/11521 , G11C16/10 , G11C16/14 , H01L29/788 , H01L27/11526
CPC classification number: G11C16/0408 , G11C16/0441 , G11C16/10 , G11C16/14 , H01L27/11521 , H01L27/11526 , H01L29/7883
Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.
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公开(公告)号：US20170243648A1
公开(公告)日：2017-08-24
申请号：US15221318
申请日：2016-07-27
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet
IPC: G11C16/04 , H01L29/788 , H01L27/115 , G11C16/10 , G11C16/14
CPC classification number: G11C16/0408 , G11C16/0441 , G11C16/10 , G11C16/14 , H01L27/11521 , H01L27/11526 , H01L29/7883
Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.
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公开(公告)号：US09728248B2
公开(公告)日：2017-08-08
申请号：US14657914
申请日：2015-03-13
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
IPC: G11C11/41 , G11C11/412 , G11C14/00 , G11C16/04 , H01L27/11
CPC classification number: G11C11/41 , G11C11/4125 , G11C14/0054 , G11C14/0063 , G11C16/0416 , H01L23/5226 , H01L27/1104 , H01L29/0847 , H01L29/42364 , H01L29/513 , H01L29/518 , H01L29/788
Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.
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公开(公告)号：US20170154683A1
公开(公告)日：2017-06-01
申请号：US15141084
申请日：2016-04-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Victorien Brecte
Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
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公开(公告)号：US09472307B1
公开(公告)日：2016-10-18
申请号：US15053989
申请日：2016-02-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
CPC classification number: G11C29/4401 , G11C7/20 , G11C16/10 , G11C16/225 , G11C16/26 , G11C16/30 , G11C2029/0407 , G11C2029/0411
Abstract: A method can be used for checking the operation of a device of electrically erasable programmable read-only memory type powered by a power supply voltage and associated with a power on reset circuit. The method includes implementation of at least one pilot operation corresponding to a phase of operation of the device that is identified as a phase that is inclined to malfunction in the event of a drop in the power supply voltage below a given value, execution of the at least one pilot operation during the operation of the memory device, and analysis of the result of the pilot operation so as to detect any malfunction not prevented by the reset circuit.
Abstract translation: 一种方法可用于检查由电源电压供电并与上电复位电路相关联的电可擦除可编程只读存储器类型的装置的操作。 该方法包括实现对应于被识别为在电源电压低于给定值的情况下倾向于故障的相位的装置的操作相位的至少一个导频操作，执行at 在存储装置的操作期间的至少一个导频操作，以及导频操作的结果的分析，以便检测不被复位电路防止的任何故障。
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