公开(公告)号：US20190027565A1

公开(公告)日：2019-01-24

申请号：US16037095

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Guilhem BOUTON ,  Pascal FORNARA ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/4238 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.

公开(公告)号：US20170148926A1

公开(公告)日：2017-05-25

申请号：US15402758

申请日：2017-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto SIMOLA ,  Pascal FORNARA

IPC: H01L29/866 ,  H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66106 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

公开(公告)号：US20240312977A1

公开(公告)日：2024-09-19

申请号：US18668639

申请日：2024-05-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Roberto SIMOLA

IPC: H01L27/01 ,  H01L21/70 ,  H10B41/41 ,  H10B41/42

CPC classification number: H01L27/016 ,  H01L21/707 ,  H10B41/41 ,  H10B41/42

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

公开(公告)号：US20230260835A1

公开(公告)日：2023-08-17

申请号：US18109569

申请日：2023-02-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Pascal FORNARA

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L21/76844 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method of manufacturing a contact on a semiconductor region includes a step of forming a stack of layers on lateral walls and at a bottom of an orifice (aligned with the semiconductor region) crossing a dielectric region along a longitudinal direction. The step of forming step is carried out from a first surface of the dielectric region and includes forming a polysilicon layer and a layer of a first metal in contact with the polysilicon layer. The first metal is preferably a metal selected from the group of transition metals and is well suited to forming with the polysilicon layer a metal silicide. The method further includes a step of performing thermal anneal causing a reaction between the first metal and the polysilicon layer to produce a layer of metal silicide. At least a portion of that layer of metal silicide extends in the longitudinal direction of the orifice.

公开(公告)号：US20210151392A1

公开(公告)日：2021-05-20

申请号：US17159698

申请日：2021-01-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Pascal FORNARA

IPC: H01L23/00 ,  G04F1/00 ,  H01L21/70 ,  H01L27/01 ,  H01L27/10

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US20210028128A1

公开(公告)日：2021-01-28

申请号：US16932082

申请日：2020-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00 ,  H01L27/11524 ,  H01L29/788

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

公开(公告)号：US20200160916A1

公开(公告)日：2020-05-21

申请号：US16747995

申请日：2020-01-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Christian RIVERO

IPC: G11C16/22 ,  G06F21/87 ,  H01L29/78 ,  H01L27/115 ,  H01L23/00 ,  H01L21/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/74 ,  H01L21/311

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

公开(公告)号：US20200075611A1

公开(公告)日：2020-03-05

申请号：US16546002

申请日：2019-08-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L27/112 ,  H01L23/58 ,  H01L23/528 ,  H01L23/522 ,  G11C17/18 ,  H01L23/525 ,  G11C17/16

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

公开(公告)号：US20200035624A1

公开(公告)日：2020-01-30

申请号：US16520458

申请日：2019-07-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice MARINET ,  Pascal FORNARA

IPC: H01L23/00 ,  H01L23/48 ,  H01L27/11521 ,  G11C16/10 ,  G11C16/14

Abstract: An attack on an integrated circuit using a beam of electrically charged particles is detected by collecting charges due to the attack using at least one electrically conductive body that is electrically coupled to the floating gate of a state transistor. Prior to the attack, the state transistor is configured to confer an initial threshold voltage. The collected charges passed to the floating gate cause a modification of the threshold voltage of the state transistor. Detection of the attack is made by determining that the threshold voltage of the state transistor is different from the initial threshold voltage.

公开(公告)号：US20190103369A1

公开(公告)日：2019-04-04

申请号：US16208253

申请日：2018-12-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Pascal FORNARA ,  Guilhem BOUTON ,  Mathieu LISART

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L23/58 ,  H01L21/8234

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.