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    Row decoder for non-volatile memory devices and related methods
    21.
    发明授权
    Row decoder for non-volatile memory devices and related methods 有权
    行解码器用于非易失性存储器件及相关方法

    公开(公告)号：US09466347B1

    公开(公告)日：2016-10-11

    申请号：US14971403

    申请日：2015-12-16

    Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Marco Pasotti ,  Vikas Rana

    IPC: G11C8/10 ,  G11C13/00

    CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069

    Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, a plurality of wordlines coupled to the array of PCM cells, and a row decoder circuit coupled to the plurality of wordlines. The row decoder circuit includes a first low voltage logic gate and a first high voltage level shifter coupled to the first low voltage logic gate. The row decoder circuit also includes a second low voltage logic gate, a second high voltage level shifter coupled to the second low voltage logic gate, and a first low voltage logic circuit coupled to the second low voltage logic gate. In addition, the row decoder circuit includes a second low voltage logic circuit coupled to the second low voltage logic gate, and a low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and an output coupled to a selected wordline.

    Abstract translation: 集成电路包括相变存储器（PCM）单元的阵列，耦合到PCM单元阵列的多个字线以及耦合到多个字线的行解码器电路。 行解码器电路包括耦合到第一低电压逻辑门的第一低电压逻辑门和第一高电压电平移位器。 行解码器电路还包括第二低电压逻辑门，耦合到第二低电压逻辑门的第二高电压电平移位器和耦合到第二低电压逻辑门的第一低电压逻辑电路。 此外，行解码器电路包括耦合到第二低电压逻辑门的第二低电压逻辑电路和具有耦合到第一和第二低电压逻辑门的输出的输入的低电压字线驱动器，以及耦合到 到一个选定的字线。

    IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY
    22.
    发明申请
    IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY 有权
    识别非易失性存储器中存储器细胞的一个条件的条件

    公开(公告)号：US20160064046A1

    公开(公告)日：2016-03-03

    申请号：US14938304

    申请日：2015-11-11

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Marcella Carissimi ,  Marco Pasotti ,  Fabio De Santis

    IPC: G11C7/06

    CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C16/0441 ,  G11C16/28

    Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.

    Abstract translation: 互补型的非易失性存储器包括存储器单元的扇区，每个单元由直接存储单元和互补存储单元形成。 当相应的存储器单元处于相同的状态并且处于写入状态时，非易失性存储器的每个扇区处于非写入状态，其中当其中的每个位置存储第一逻辑值或第二逻辑值时， 位置分别处于不同状态的第一组合或处于不同状态的第二组合中。 选择扇区，并且确定处于编程状态的多个存储单元和被擦除状态的多个存储单元。 根据该信息，通过编程状态下的存储单元的数量和被擦除状态的存储单元的数量之间的比较来识别所选扇区的状态。

    Memory device and method for in-memory computing
    24.
    发明授权
    Memory device and method for in-memory computing 有权

    公开(公告)号：US11756615B2

    公开(公告)日：2023-09-12

    申请号：US17462250

    申请日：2021-08-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marcella Carissimi ,  Marco Pasotti ,  Roberto Antonio Canegallo

    IPC: G11C11/00 ,  G11C13/00 ,  G06N3/02

    CPC classification number: G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0004 ,  G11C13/0038 ,  G06N3/02

    Abstract: An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.

    Positive and negative charge pump control
    25.
    发明授权
    Positive and negative charge pump control 有权

    公开(公告)号：US11611275B2

    公开(公告)日：2023-03-21

    申请号：US17866372

    申请日：2022-07-15

    Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

    Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

    IPC: H02M3/07 ,  G11C5/14

    Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

    MEMORY DEVICE AND METHOD FOR IN-MEMORY COMPUTING
    26.
    发明申请
    MEMORY DEVICE AND METHOD FOR IN-MEMORY COMPUTING 有权

    公开(公告)号：US20220068380A1

    公开(公告)日：2022-03-03

    申请号：US17462250

    申请日：2021-08-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marcella Carissimi ,  Marco Pasotti ,  Roberto Canegallo

    IPC: G11C13/00

    Abstract: An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.

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