公开(公告)号：US11289500B2

公开(公告)日：2022-03-29

申请号：US17001035

申请日：2020-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Dongku Kang

IPC: G11C16/04 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US11282827B2

公开(公告)日：2022-03-22

申请号：US16940333

申请日：2020-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Dongku Kang

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L25/00 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556

Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region including second metal pads. The memory cell region includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US11227860B2

公开(公告)日：2022-01-18

申请号：US16942854

申请日：2020-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L23/522 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: A memory device includes a memory cell chip, a peripheral circuit chip, and a routing wire. The memory cell chip includes a memory cell array disposed on a first substrate, and a first metal pad on a first uppermost metal layer. The peripheral circuit chip includes circuit devices disposed on a second substrate, and a second metal pad on a second uppermost metal layer of the peripheral circuit chip. The memory cell chip and the peripheral circuit chip are vertically connected to each other by the first metal pad and the second metal pad in a bonding area. The routing wire is electrically connected to the peripheral circuit and is disposed in the first uppermost metal layer or the second uppermost metal layer and is disposed in a non-bonding area in which the memory cell chip and the peripheral circuit chip are not electrically connected to each other.

公开(公告)号：US20210124527A1

公开(公告)日：2021-04-29

申请号：US16892574

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G05D1/00

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.

公开(公告)号：US10546875B2

公开(公告)日：2020-01-28

申请号：US15996483

申请日：2018-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Pansuk Kwak ,  Chaehoon Kim ,  Hongsoo Jeon ,  Jeunghwan Park ,  Bongsoon Lim

IPC: H01L27/11 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/24 ,  H01L27/1157 ,  G11C16/08

Abstract: At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.

公开(公告)号：US20190130974A1

公开(公告)日：2019-05-02

申请号：US15992840

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dong-Kil Yun ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C14/00 ,  H01L27/11578 ,  H01L27/108 ,  H01L27/1157

CPC classification number: G11C14/0018 ,  G11C11/005 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/10808 ,  H01L27/10847 ,  H01L27/1157 ,  H01L27/11578

Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.

公开(公告)号：US11723208B2

公开(公告)日：2023-08-08

申请号：US17695186

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Dongku Kang

IPC: G11C11/00 ,  H10B43/40 ,  G11C16/08 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  G11C7/18 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US11664361B2

公开(公告)日：2023-05-30

申请号：US17577647

申请日：2022-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Joo-Yong Park ,  Daeseok Byeon

IPC: H01L25/18 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.

公开(公告)号：US11430806B2

公开(公告)日：2022-08-30

申请号：US16878756

申请日：2020-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Dongku Kang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

公开(公告)号：US11430804B2

公开(公告)日：2022-08-30

申请号：US16809059

申请日：2020-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Dongku Kang

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.