公开(公告)号：US11550498B2

公开(公告)日：2023-01-10

申请号：US17030635

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung Kim ,  Jangwoo Lee ,  Seonkyoo Lee ,  Chiweon Yoon ,  Jeongdon Ihm

IPC: G06F3/06 ,  G06K9/62

Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

公开(公告)号：US11372593B2

公开(公告)日：2022-06-28

申请号：US17168620

申请日：2021-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonkyoo Lee ,  Jeongdon Ihm ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G06F3/06 ,  G11C16/26 ,  G06F1/06 ,  G11C16/04 ,  G11C16/10 ,  G06F13/16

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

公开(公告)号：US20220148630A1

公开(公告)日：2022-05-12

申请号：US17352527

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G11C7/10 ,  H03K19/00

Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.

公开(公告)号：US20220101893A1

公开(公告)日：2022-03-31

申请号：US17470579

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyeon PARK ,  Byunghoon Jeong ,  Chiweon Yoon

IPC: G11C7/10 ,  G11C7/20 ,  G11C8/06

Abstract: A memory chip, a memory controller, and an operating method of the memory chip are provided. The memory chip includes a plurality of pins; and an interface circuit configured to receive a swap command set from a memory controller through the plurality of pins, obtain a swap command and a swap address from the swap command set, generate a swap enable signal based on the swap command and the swap address, and swap and output a data signal according to the swap enable signal.

公开(公告)号：US12217793B2

公开(公告)日：2025-02-04

申请号：US17852035

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunjin Song ,  Kyoungtae Kang ,  Sanglok Kim ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4094

Abstract: A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.

公开(公告)号：US12190942B2

公开(公告)日：2025-01-07

申请号：US17863037

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

公开(公告)号：US20240347080A1

公开(公告)日：2024-10-17

申请号：US18406726

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsuk Kang ,  Jeongsu Lee ,  Eunji An ,  Jungjune Park ,  Chiweon Yoon

IPC: G11C5/14

CPC classification number: G11C5/147

Abstract: A semiconductor device includes a first pull-up circuit connected between a first power node supplying a first power voltage and an output node through which a signal is output, and including a plurality of NMOS transistors; a second pull-up circuit connected in parallel to the first pull-up circuit between the first power node and the output node and including a plurality of PMOS transistors; and a control circuit outputting a first pull-up code to the first pull-up circuit and outputting the second pull-up code to the second pull-up circuit. In a first operating mode, the signal swings between a first low level lower than the first power voltage, and a first high level lower than ½ times the first power voltage, resistance of the first pull-up circuit is determined based on the first pull-up code, and resistance of the second pull-up circuit is determined based on the second pull-up code.

公开(公告)号：US20240321330A1

公开(公告)日：2024-09-26

申请号：US18611213

申请日：2024-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anil KAVALA ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

IPC: G11C7/22 ,  G11C7/14 ,  H03L7/099

CPC classification number: G11C7/222 ,  G11C7/14 ,  H03L7/0998

Abstract: A storage device includes a buffer chip and a memory device. The memory device transmits a random data signal and a data strobe signal to the buffer chip based on a clock signal received from the buffer chip. The buffer chip includes a delay circuit that delays the data strobe signal by a delay time to generate a delayed data strobe signal, a sampler that receives the delayed data strobe signal from the delay circuit and samples the random data signal based on the delayed data strobe signal to generate sampled data, a comparator that compares internal data with the sampled data to generate a comparison result, and a counter module that receives the comparison result from the comparator and determines a target delay based on the comparison result. The buffer chip delays the delayed data strobe signal based on the target delay.

公开(公告)号：US20240312551A1

公开(公告)日：2024-09-19

申请号：US18529619

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

IPC: G11C29/46 ,  G11C29/12 ,  G11C29/38

CPC classification number: G11C29/46 ,  G11C29/1201 ,  G11C29/38 ,  G11C2029/4002

Abstract: A storage device includes a plurality of memory chips, a buffer chip connected to the plurality of memory chips, and a controller connected to the buffer chip. The buffer chip is configured to periodically receive a first command from the controller, and perform a DQS oscillator enable operation in response to the first command. At least one memory chip among the plurality of memory chips and the buffer chip are configured to perform write training or read training when the DQS oscillator enable operation is performed.

公开(公告)号：US20240242765A1

公开(公告)日：2024-07-18

申请号：US18382325

申请日：2023-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jayang Yoon ,  Chihyun Kim ,  Sangsoo Park ,  Junehong Park ,  Chiweon Yoon ,  Hyeongdo Choi

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/30

Abstract: A non-volatile memory device includes a memory cell array including memory cells coupled to word lines, a boost circuit that receives an external power supply voltage and generate a boosted voltage based on the external power supply voltage, a regulator that generates a regulated voltage based on the external power supply voltage, and a control logic that controls word line voltages provided to the word lines. The control logic performs plural program loops in a program operation for the memory cell array. The control logic provides an adjacent word line voltage to an adjacent word line that is adjacent to a selected word line. In a first section of the program loops, the control logic provides the regulated voltage as the adjacent word line voltage, and in a second section of the program loops, the control logic provides the boosted voltage as the adjacent word line voltage.