公开(公告)号：US11593199B2

公开(公告)日：2023-02-28

申请号：US17562505

申请日：2021-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US20220121518A1

公开(公告)日：2022-04-21

申请号：US17562505

申请日：2021-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US10929225B2

公开(公告)日：2021-02-23

申请号：US16894115

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

IPC: G11C29/52 ,  G06F11/10 ,  G06F3/06 ,  G11C29/04 ,  G11C29/00

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

公开(公告)号：US10446216B2

公开(公告)日：2019-10-15

申请号：US15134637

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Oh ,  Ho-Young Song ,  Do-Yeon Kim

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/4076

Abstract: Embedded refresh controllers included in memory devices and memory devices including the embedded refresh controllers are provided. The embedded refresh controllers may include a refresh counter and an address generator. The refresh counter may generate a counter refresh address signal in response to a counter refresh signal such that the counter refresh address signal may represent a sequentially changing address. The address generator may store information with respect to a hammer address that is accessed intensively and may generates a hammer refresh address signal in response to a hammer refresh signal such that the hammer refresh address signal may represent an address of a row that is physically adjacent to a row of the hammer address. Loss of cell data may be reduced and performance of the memory device may be enhanced by detecting the intensively-accessed hammer address and performing the refresh operation based on the detected hammer address efficiently.

公开(公告)号：US10416896B2

公开(公告)日：2019-09-17

申请号：US15603255

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Il O ,  Nam Sung Kim ,  Young-Hoon Son ,  Chan-Kyung Kim ,  Ho-Young Song ,  Jung Ho Ahn ,  Sang-Joon Hwang

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US10347355B2

公开(公告)日：2019-07-09

申请号：US15795595

申请日：2017-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G06F11/20 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/00 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/36 ,  G11C29/42

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US09601216B2

公开(公告)日：2017-03-21

申请号：US14970983

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Ryu ,  Ho-Young Song ,  Yun-Young Lee

IPC: G11C29/40 ,  G11C29/04 ,  G11C29/00 ,  G11C17/16 ,  G11C17/14 ,  G11C17/18 ,  G11C8/10 ,  G06F11/00 ,  G11C17/00

CPC classification number: G11C29/40 ,  G06F11/006 ,  G11C8/10 ,  G11C17/00 ,  G11C17/143 ,  G11C17/16 ,  G11C17/18 ,  G11C29/04 ,  G11C29/76

Abstract: Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays.

公开(公告)号：US09165673B2

公开(公告)日：2015-10-20

申请号：US13795567

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Yu ,  Ho-Young Song ,  Sung-Min Seo ,  Sang-Joon Hwang

IPC: G11C17/00 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C17/18

Abstract: A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.

Abstract translation: 半导体存储器件包括：存储单元阵列，被配置为存储包括验证码的数据; 感测单元，被配置为感测存储的包括验证码的数据; 以及验证单元，被配置为基于感测条件来确定所述感测单元是否能够感测所存储的数据，其中所述验证单元被配置为基于所述感测条件来确定所述感测单元是否能够感测所存储的数据，以及 由感测单元感测的验证码的值。