公开(公告)号：US20210408040A1

公开(公告)日：2021-12-30

申请号：US17473006

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20210151460A1

公开(公告)日：2021-05-20

申请号：US16928306

申请日：2020-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungdong KIM ,  Younghwan SON ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11526

Abstract: A vertical-type nonvolatile memory device including: a substrate including a cell array area and an extension area, the extension area extending in a first direction from the cell array area and including contacts; a channel structure extending in a vertical direction from the substrate; a first stack structure including gate electrode layers and interlayer insulating layers alternately stacked along sidewalls of the channel structure; a plurality of division areas extending in the first direction and dividing the cell array area and the extension area in a second direction perpendicular to the first direction; in the extension area, two insulating layer dams are arranged between two division areas adjacent to each other; a second stack structure including sacrificial layers and interlayer insulating layers alternately stacked on the substrate between the two insulating layer dams; and an electrode pad connected to a first gate electrode layer in the extension area.

公开(公告)号：US20250096135A1

公开(公告)日：2025-03-20

申请号：US18962181

申请日：2024-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun LEE ,  Seokjung YUN ,  Chang-Sup LEE ,  Seong Soon CHO ,  Jeehoon HAN

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/20 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US20250056808A1

公开(公告)日：2025-02-13

申请号：US18931606

申请日：2024-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong CHUNG ,  Jaeryong SIM ,  Kwangyoung JUNG ,  Jeehoon HAN

IPC: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

公开(公告)号：US20240347455A1

公开(公告)日：2024-10-17

申请号：US18508757

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-gn YUN ,  Jeehoon HAN ,  Hyunho KIM

IPC: H01L23/528 ,  G11C5/06 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  G11C5/063 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/0651

Abstract: A semiconductor device including a first conductive pattern having a first connection part and a plurality of first branch parts connected to the first connection part, a second conductive pattern having a second connection part and a plurality of second branch parts connected to the second connection part, a first memory channel structure in contact with a corresponding one of the first branch parts and a corresponding one of the second branch parts, and a gate cutting pattern in contact with the corresponding one of the second branch parts and the first connection part may be provided. The first conductive pattern and the second conductive pattern may be spaced apart from each other.

公开(公告)号：US20240113160A1

公开(公告)日：2024-04-04

申请号：US18303205

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juseong MIN ,  Kyeonghoon PARK ,  Jae-Bok BAEK ,  Donghyuck JANG ,  Jeehoon HAN ,  Taeyoon HONG

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/4236

Abstract: A semiconductor device include a substrate including a plurality of protrusions protruding from an upper surface thereof and arranged two-dimensionally in a first direction and a second direction intersecting each other, a first trench provided between the protrusions in the first direction, and a second trench provided between the protrusions in the second direction, a first device isolation layer filling the first trench, gate patterns disposed on the protrusions in the second direction, upper surfaces of the protrusions exposed at both sides of the gate patterns, respectively, and a second device isolation layer filling a space between the gate patterns in the second direction and the second trench, and each of the gate patterns has a first sidewall adjacent to the second trench and aligned with an inner wall of the second trench.

公开(公告)号：US20240032298A1

公开(公告)日：2024-01-25

申请号：US18177335

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon PARK ,  Juseong MIN ,  Jaebok BAEK ,  Donghyuck JANG ,  Sanghun CHUN ,  Jeehoon HAN ,  Taeyoon HONG

IPC: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  G11C5/06

CPC classification number: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  G11C5/06

Abstract: A semiconductor device includes a peripheral circuit structure including circuits, wiring layers, and via contacts, a plate common source line covering the peripheral circuit structure, an insulating plug passing through the plate common source line, a lateral insulating spacer between the peripheral circuit structure and the plate common source line, a memory stack structure including gate lines on the plate common source line, a through contact passing through at least one of the gate lines and the insulating plug, the through contact being connected to a first via contact of the via contacts, and a source line contact passing through the lateral insulating spacer, the source line contact being between a second via contact of the via contacts and the plate common source line, wherein a width of the first via contact is greater than a width of the insulating plug in a lateral direction.

公开(公告)号：US20230186990A1

公开(公告)日：2023-06-15

申请号：US17876694

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Yoon KIM ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: G11C16/04 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes: a stack structure including a ground selection line, first word lines, second word lines, and a string selection line, which are sequentially stacked on a substrate; vertical channel structures penetrating the stack structure and arranged to form a plurality of columns; a lower separation structure crossing a lower portion of the stack structure in a first direction and dividing the ground selection line along a second direction intersecting the first direction; and first and second upper separation structures crossing an upper portion of the stack structure in the first direction and dividing the string selection line along the second direction, wherein the lower separation structure and the first upper separation structure are vertically overlapped with one of the columns of the vertical channel structures, and the second upper separation structures are provided between the vertical channel structures.

公开(公告)号：US20220093631A1

公开(公告)日：2022-03-24

申请号：US17352862

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Shinhwan KANG ,  Jeehoon HAN

IPC: H01L27/11575 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.

公开(公告)号：US20210013304A1

公开(公告)日：2021-01-14

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon RYU ,  Kiyoon KANG ,  Seogoo KANG ,  Shinhwan KANG ,  Jesuk MOON ,  Byunggon PARK ,  Jaeryong SIM ,  Jinsoo LIM ,  Jisung CHEON ,  Jeehoon HAN

IPC: H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.