公开(公告)号：US11482670B2

公开(公告)日：2022-10-25

申请号：US16909218

申请日：2020-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiho Park ,  Kwangmin Park ,  Jeonghee Park ,  Changyup Park ,  Sukhwan Chung

IPC: H01L45/00

Abstract: A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 μs to about 54 μs.

公开(公告)号：US11387410B2

公开(公告)日：2022-07-12

申请号：US16800123

申请日：2020-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghee Park ,  Kwangmin Park ,  Jiho Park ,  Gyuhwan Oh ,  Jungmoo Lee ,  Hideki Horii

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a base structure comprising a semiconductor substrate, a first conductive structure disposed on the base structure, and extending in a first direction, the first conductive structure including lower layers, and at least one among the lower layers including carbon, and a data storage pattern disposed on the first conductive structure. The semiconductor device further includes an intermediate conductive pattern disposed on the data storage pattern, and including intermediate layers, at least one among the intermediate layers including carbon, a switching pattern disposed on the intermediate conductive pattern, and a switching upper electrode pattern disposed on the switching pattern, and including carbon. The semiconductor device further includes a second conductive structure disposed on the switching upper electrode pattern, and extending in a second direction intersecting the first direction, and a hole spacer disposed on a side surface of the data storage pattern.

公开(公告)号：US20210111260A1

公开(公告)日：2021-04-15

申请号：US17129667

申请日：2020-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20200258994A1

公开(公告)日：2020-08-13

申请号：US16859437

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L29/51 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/06 ,  H01L21/3213

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：USRE46389E1

公开(公告)日：2017-05-02

申请号：US14686984

申请日：2015-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

IPC: H01L21/8247 ,  H01L21/28

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

公开(公告)号：US20150041882A1

公开(公告)日：2015-02-12

申请号：US14493849

申请日：2014-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyul Lee ,  Bumsu Kim ,  Kwangmin Park ,  Hyun Park ,  Jae-young Ahn ,  Dongchul Yoo ,  Jongsik Chun ,  Kihyun Hwang

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

Abstract translation: 三维（3D）半导体存储器件包括电极分离图案，堆叠结构，数据存储层和沟道结构。 电极分离图案设置在基板上。 堆叠结构设置在电极分离图案的侧壁上。 堆叠结构包括与电极分离图案的侧壁相对的波纹状侧壁。 电极分离图案的侧壁垂直于基板。 数据存储层设置在波纹侧壁上。 通道结构设置在电荷存储层上。

公开(公告)号：US11888042B2

公开(公告)日：2024-01-30

申请号：US18094484

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L27/06 ,  H01L29/423 ,  H01L21/3213 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US11581367B2

公开(公告)日：2023-02-14

申请号：US17209660

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Ahn ,  Segab Kwon ,  Chungman Kim ,  Kwangmin Park ,  Zhe Wu ,  Seunggeun Yu ,  Wonjun Lee ,  Jabin Lee ,  Jinwoo Lee

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

公开(公告)号：US11574956B2

公开(公告)日：2023-02-07

申请号：US17314638

申请日：2021-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiho Park ,  Kwangmin Park ,  Wonjun Park ,  Jeonghee Park ,  Changyup Park ,  Hwasung Chae

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.

公开(公告)号：US09564499B2

公开(公告)日：2017-02-07

申请号：US13972533

申请日：2013-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Soo Seol ,  Chanjin Park ,  Ki-Hyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Ju-Yul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/115 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Abstract translation: 三维半导体存储器件及其制造方法。 三维半导体器件包括具有布置在衬底上的顺序层叠电极的电极结构，穿透电极结构的半导体图案，以及插入在半导体图案和电极结构之间的包括第一图案和第二图案的存储元件，第一 垂直延伸以横过电极的图案和第二图案水平延伸以跨越半导体图案。