公开(公告)号：US20240178213A1

公开(公告)日：2024-05-30

申请号：US18226037

申请日：2023-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon Yu ,  Pansuk Kwak

IPC: H01L27/02 ,  H01L21/02 ,  H01L21/302 ,  H01L21/768 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/0207 ,  H01L21/02403 ,  H01L21/302 ,  H01L21/76897 ,  H01L27/0928 ,  H01L29/0615

Abstract: A semiconductor device includes a substrate, a P-well region, a first N-type metal oxide semiconductor (NMOS) transistor provided in the P-well region, a second NMOS transistor provided on the substrate, and a common body bias region provided between the first NMOS transistor and the second NMOS transistor and contacting both the P-well region and the substrate.

公开(公告)号：US11875855B2

公开(公告)日：2024-01-16

申请号：US17746393

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Pansuk Kwak

IPC: G11C16/08 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.

公开(公告)号：US20220115393A1

公开(公告)日：2022-04-14

申请号：US17345832

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon Yu ,  Pansuk Kwak

IPC: H01L27/11573 ,  H01L21/66 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.

公开(公告)号：US11289500B2

公开(公告)日：2022-03-29

申请号：US17001035

申请日：2020-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Dongku Kang

IPC: G11C16/04 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US10546875B2

公开(公告)日：2020-01-28

申请号：US15996483

申请日：2018-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Pansuk Kwak ,  Chaehoon Kim ,  Hongsoo Jeon ,  Jeunghwan Park ,  Bongsoon Lim

IPC: H01L27/11 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/24 ,  H01L27/1157 ,  G11C16/08

Abstract: At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.

公开(公告)号：US20190130974A1

公开(公告)日：2019-05-02

申请号：US15992840

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dong-Kil Yun ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C14/00 ,  H01L27/11578 ,  H01L27/108 ,  H01L27/1157

CPC classification number: G11C14/0018 ,  G11C11/005 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/10808 ,  H01L27/10847 ,  H01L27/1157 ,  H01L27/11578

Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.

公开(公告)号：US12293791B2

公开(公告)日：2025-05-06

申请号：US18504093

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

公开(公告)号：US12205643B2

公开(公告)日：2025-01-21

申请号：US18407399

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Pansuk Kwak ,  Daeseok Byeon

IPC: G11C7/24 ,  G11C5/06 ,  G11C13/00 ,  G11C16/10

Abstract: Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

公开(公告)号：US20240306394A1

公开(公告)日：2024-09-12

申请号：US18434356

申请日：2024-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungun Lee ,  Pansuk Kwak ,  Changyeon Yu

IPC: H10B43/40 ,  G11C16/08 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  G11C16/08

Abstract: A memory device includes a stack structure, in which a common source line is formed, and a peripheral circuit structure overlapping the stack structure when viewed in plan view and comprising a common source line driver configured to discharge the common source line. The common source line driver includes a first common source line driving unit, electrically connected to the common source line through a first network and configured to discharge the common source line, and a second common source line driving unit electrically connected to the common source line through a second network, different from the first network, and configured to discharge the common source line. The first common source line driving unit and the second common source line driving unit are controlled independently of each other.

公开(公告)号：US20240105268A1

公开(公告)日：2024-03-28

申请号：US18529897

申请日：2023-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.