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    Three-dimensional nonvolatile memory and operating method of three-dimensional nonvolatile memory
    21.
    发明授权
    Three-dimensional nonvolatile memory and operating method of three-dimensional nonvolatile memory 有权
    三维非易失性存储器和三维非易失性存储器的操作方法

    公开(公告)号：US09412450B2

    公开(公告)日：2016-08-09

    申请号：US14155877

    申请日：2014-01-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gilsung Lee ,  Jaehoon Jang ,  Kihyun Kim ,  Sunil Shim

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/26

    CPC classification number: G11C16/0483 ,  G11C16/26

    Abstract: Disclosed is a nonvolatile memory having a memory cell array including a plurality of cell strings, each cell string including memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the memory cells and the substrate, and a string selection transistor between the memory cells and a bit line. The memory also includes an address decoder connected to the memory cells, the string selection transistors, and the ground selection transistors, and configured to apply a ground voltage to the string selection lines, word lines, and ground selection line. Further, the memory includes a read/write circuit connected to the string selection transistors through bit lines, and at least one first memory cell maintains a threshold voltage higher than a threshold voltage distribution corresponding to an erase state.

    Abstract translation: 公开了具有包括多个单元串的存储单元阵列的非易失性存储器，每个单元串包括沿垂直于衬底的方向堆叠的存储单元，存储单元和衬底之间的接地选择晶体管，以及串选择晶体管， 存储单元和位线。 存储器还包括连接到存储单元的地址解码器，串选择晶体管和接地选择晶体管，并且被配置为对串选择线，字线和地选择线施加接地电压。 此外，存储器包括通过位线连接到串选择晶体管的读/写电路，并且至少一个第一存储单元维持高于对应于擦除状态的阈值电压分布的阈值电压。

    Nonvolatile memory devices and operating methods thereof
    22.
    发明授权
    Nonvolatile memory devices and operating methods thereof 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US08923060B2

    公开(公告)日：2014-12-30

    申请号：US13721963

    申请日：2012-12-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunil Shim ,  Jaehoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

    IPC: G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  H01L27/115 ,  G11C16/34 ,  G11C16/30

    CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

    Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array including a plurality of memory cells; a word line driver configured to at least one of select and unselect a plurality of word lines connected with the plurality of memory cells, respectively, and to supply voltages to the plurality of word lines; and a read/write circuit configured to apply bias voltages to a plurality of bit lines connected with the plurality of memory cells. The read/write circuit may be configured to adjust levels of the bias voltages applied to the plurality of bit lines according to location of a selected word line among the plurality of word lines.

    Abstract translation: 根据发明构思的示例实施例，非易失性存储器件包括包括多个存储器单元的存储单元阵列; 字线驱动器，被配置为分别选择和取消选择与所述多个存储器单元连接的多个字线中的至少一个，并向所述多个字线提供电压; 以及读/写电路，被配置为向与多个存储单元连接的多个位线施加偏置电压。 读/写电路可以被配置为根据多个字线中所选择的字线的位置来调整施加到多个位线的偏置电压的电平。

    SEMICONDUCTOR DEVICE
    27.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240179914A1

    公开(公告)日：2024-05-30

    申请号：US18510209

    申请日：2023-11-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chulmin Choi ,  Sunil Shim ,  Joohyun Lim

    IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

    CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

    Abstract: A semiconductor device includes a gate electrode structure including first to fourth gate electrodes, a first memory channel structure extending through the first to third gate electrodes, a second memory channel structure contacting an upper surface of the first memory channel structure and extending through the fourth gate electrode, and a first contact plug including a lower portion extending partially through the gate electrode structure and an upper portion on and contacting an upper surface of the lower portion. The lower portion of the first contact plug has a varying width, and the upper portion of the first contact plug has a width gradually increasing from a bottom toward a top thereof. The lower portion of the first contact plug extends through the first, second and third gate electrodes, and is electrically insulated from the first and second gate electrodes, and is electrically connected to the third gate electrode.

    SEMICONDUCTOR DEVICE AND A DATA STORAGE SYSTEM INCLUDING THE SAME
    30.
    发明申请
    SEMICONDUCTOR DEVICE AND A DATA STORAGE SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220254807A1

    公开(公告)日：2022-08-11

    申请号：US17507929

    申请日：2021-10-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongsoo KIM ,  Sunil Shim ,  Juyoung Lim ,  Wonseok Cho

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

    Abstract: A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level.

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