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21.发明授权公开(公告)号：US12198782B2
公开(公告)日：2025-01-14
申请号：US18449864
申请日：2023-08-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Min Hwi Kim , Ji-Sang Lee
Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.
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22.发明公开公开(公告)号：US20240363172A1
公开(公告)日：2024-10-31
申请号：US18509021
申请日：2023-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjeong Heo , Jaehue Shin , Daeseok Byeon , Yongsung Cho
CPC classification number: G11C16/24 , G11C16/0483
Abstract: A nonvolatile memory device includes a plurality of tri-state latches, a sensing node circuit configured to electrically couple a sensing node therein to a bitline of the memory device, a transfer node circuit configured to electrically couple a transfer node therein to the plurality of tri-state latches, and a node connection circuit configured to electrically connect the transfer node to the sensing node. In addition, the transfer node circuit and the node connection circuit are collectively configured to simultaneously reflect data stored in at least two of the plurality of tri-state latches to the sensing node, in response to a dump sequence operation.
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公开(公告)号：US12057173B2
公开(公告)日：2024-08-06
申请号：US17836453
申请日：2022-06-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho
Abstract: A memory device includes a memory cell array, and a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a plurality of page buffers arranged in correspondence with the bit lines and each of which includes a sensing node. The plurality of page buffers include a first page buffer, and the first page buffer includes: a first sensing node configured to sense data by corresponding to a first metal wire at a lower metal layer; and a second metal wire electrically connected to the first metal wire and at an upper metal layer located above the lower metal layer, and a boost node corresponding to a third metal wire adjacent to the second metal wire of the upper metal layer and configured to control a boost-up and a boost-down of a voltage of the first sensing node.
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公开(公告)号：US11437088B2
公开(公告)日：2022-09-06
申请号：US17239655
申请日：2021-04-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngjae Kim , Jincheol Kim , Ahreum Kim , Homoon Shin , Dooho Cho , Yongsung Cho
IPC: G11C11/408 , G11C11/4074 , G11C11/4093 , G11C5/06
Abstract: A nonvolatile memory includes; a memory cell array including memory cells commonly connected to a first signal line, a first row decoder including a first pass transistor configured to provide a driving voltage to one end of the first signal line, and a second row decoder including a second pass transistor configured to provide the driving voltage to an opposing end of the first signal line. An ON-resistance of the first pass transistor is different from an ON-resistance of the second pass transistor. A first wiring line having a first resistance connects the first pass transistor and the one end of the first signal line and a second wiring line having a second resistance different from the first resistance connects the second pass transistor and the opposing end of the first signal line.
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公开(公告)号：US20220068322A1
公开(公告)日：2022-03-03
申请号：US17222024
申请日：2021-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Jinwoo Park , Hyunjun Yoon , Yoonhee Choi
Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.
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Patent Agency Ranking
公开(公告)号：US09064545B2
公开(公告)日：2015-06-23
申请号：US13721859
申请日：2012-12-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsung Cho , Kihwan Choi , Il Han Park , Kiwhan Song , Sangyong Yoon
CPC classification number: G11C7/04 , G11C16/0483 , G11C16/10
Abstract: A method of programming a nonvolatile memory device comprises determining a temperature condition of the nonvolatile memory device, determining a program pulse period according to the temperature condition, supplying a program voltage to a selected word line using the program pulse period, and supplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line.
Abstract translation: 非易失性存储器件的编程方法包括：确定非易失性存储器件的温度状态，根据温度条件确定编程脉冲周期，使用编程脉冲周期向选定字线提供编程电压，并提供通过电压 在将程序电压提供给所选择的字线的同时，将其作为未选择的字线。
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公开(公告)号：US12040799B2
公开(公告)日：2024-07-16
申请号：US18154966
申请日：2023-01-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok Nam , Jaehyuk Yang , Yongsung Cho
Abstract: A clock generating device includes a first voltage output circuit configured to output a first voltage corresponding to a power supply voltage in response to a preliminary clock signal, a clock output circuit configured to generate the preliminary clock signal and a final clock signal at a period corresponding to a difference between the first voltage and a negative feedback voltage, a negative feedback voltage generating circuit configured to generate the negative feedback voltage from a reference value corresponding to a frequency of the final clock signal and a second voltage and filtered to a uniform voltage level, and a second voltage output circuit configured to output the second voltage to the negative feedback voltage generating unit, the second voltage having lower sensitivity of fluctuations in the power supply voltage than the first voltage.
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公开(公告)号：US12002518B2
公开(公告)日：2024-06-04
申请号：US17710283
申请日：2022-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsung Cho , Kyoman Kang , Minhwi Kim , Ilhan Park , Jinyoung Chun
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/26
Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.
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公开(公告)号：US20240145013A1
公开(公告)日：2024-05-02
申请号：US18367799
申请日：2023-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Insu Kim , Daeseok Byeon
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/30 , G11C16/3459 , G11C16/32
Abstract: A memory device includes a memory cell array, and a page buffer circuit including a plurality of page buffers selectively connected to memory cells via a plurality of bit lines, each of the plurality of page buffers including a sensing node. The sensing nodes may be charged to different levels during verification of programming states of the memory cells. For example, a first sensing node of a first page buffer connected to a first memory cell targeted for programming to a first program state from among the plurality of page buffers is precharged to a first level in a first precharge period during verification of the first program state. A second sensing node of a second page buffer connected to a second memory cell targeted for programming to a second program state charged to a second level during verification of the second program state, wherein the second level is different from the first level.
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公开(公告)号：US20240105267A1
公开(公告)日：2024-03-28
申请号：US18201331
申请日：2023-05-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Inho Kang , Daeseok Byeon , Beakhyung Cho , Min-Hwi Kim , Yongsung Cho , Gyosoo Choo
CPC classification number: G11C16/24 , G11C16/0483 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/41 , H10B43/40 , H10B80/00 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.
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