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    BACKGROUND READS TO CONDITION PROGRAMMED SEMICONDUCTOR MEMORY CELLS
    21.
    发明申请
    BACKGROUND READS TO CONDITION PROGRAMMED SEMICONDUCTOR MEMORY CELLS 审中-公开

    公开(公告)号：US20180225164A1

    公开(公告)日：2018-08-09

    申请号：US15498595

    申请日：2017-04-27

    Applicant: Seagate Technology, LLC

    Inventor： Antoine Khoueir ,  Stacey Secatch ,  Kevin Gomez ,  Ryan Goss

    IPC: G06F11/07 ,  G11C16/16 ,  G11C16/34 ,  G11C16/26

    CPC classification number: G06F11/076 ,  G06F11/073 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459

    Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

    DYNAMICALLY MODIFYING A BOUNDARY OF A DEEP LEARNING NETWORK
    26.
    发明申请
    DYNAMICALLY MODIFYING A BOUNDARY OF A DEEP LEARNING NETWORK 审中-公开
    动态修改深度学习网络的边界

    公开(公告)号：US20160098646A1

    公开(公告)日：2016-04-07

    申请号：US14506972

    申请日：2014-10-06

    Applicant: Seagate Technology LLC

    Inventor： Kevin Arthur Gomez ,  Frank Dropps ,  Ryan James Goss ,  Jon Trantham ,  Antoine Khoueir

    IPC: G06N99/00 ,  H04L29/08 ,  G06N3/08

    CPC classification number: G06N20/00 ,  G06N3/0454 ,  G06N7/005 ,  H04L67/10 ,  H04L67/141

    Abstract: A connection between a user device and a network server is established. Via the connection, a deep learning network is formed for a processing task. A first portion of the deep learning network operates on the user device and a second portion of the deep learning network operates on the network server. Based on cooperation between the user device and the network server, a boundary between the first portion and the second portion of the deep learning network is dynamically modified based on a change in a performance indicator that could affect the processing task

    Abstract translation: 建立用户设备与网络服务器之间的连接。 通过连接，形成了用于处理任务的深度学习网络。 深度学习网络的第一部分在用户设备上操作，并且深度学习网络的第二部分在网络服务器上操作。 基于用户设备和网络服务器之间的协作，基于可能影响处理任务的性能指标的变化来动态地修改深度学习网络的第一部分和第二部分之间的边界

    DATA PROTECTION FOR UNEXPECTED POWER LOSS
    27.
    发明申请
    DATA PROTECTION FOR UNEXPECTED POWER LOSS 有权
    数据保护意外的电力损失

    公开(公告)号：US20150155050A1

    公开(公告)日：2015-06-04

    申请号：US14616424

    申请日：2015-02-06

    Applicant: Seagate Technology LLC

    Inventor： Jon Trantham ,  Michael Joseph Steiner ,  Antoine Khoueir

    IPC: G11C16/34 ,  G11C11/56

    CPC classification number: G11C16/3418 ,  G11C5/143 ,  G11C11/5621 ,  G11C16/14 ,  G11C16/3409

    Abstract: A data storage device receives a write data command and data. The data is stored in a buffer of the data storage device. The data storage device issues a command complete status indication. After the command complete status indication is issued, the data are stored in a primary memory of the data storage device. The primary memory comprises a first type of non-volatile memory and the buffer comprises a second type of non-volatile memory that is different from the first type of non-volatile memory.

    Abstract translation: 数据存储装置接收写数据命令和数据。 数据存储在数据存储装置的缓冲器中。 数据存储设备发出命令完成状态指示。 在发出命令完成状态指示之后，将数据存储在数据存储设备的主存储器中。 主存储器包括第一类型的非易失性存储器，并且缓冲器包括与第一类型的非易失性存储器不同的第二类型的非易失性存储器。

    Cross-point resistive-based memory architecture
    28.
    发明授权
    Cross-point resistive-based memory architecture 有权
    交叉点电阻式存储架构

    公开(公告)号：US08949567B2

    公开(公告)日：2015-02-03

    申请号：US13777137

    申请日：2013-02-26

    Applicant: Seagate Technology LLC

    Inventor： Antoine Khoueir ,  Jon D. Trantham ,  Kevin Gomez ,  Ara Patapoutian

    IPC: G06F13/00 ,  G06F12/00

    CPC classification number: G06F12/00 ,  G06F12/0238

    Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.

    Abstract translation: 多个可寻址存储器块各自包括一个或多个交叉点阵列。 每个阵列包括多个非易失性电阻变化存储单元。 控制器被配置为耦合到阵列和主机系统。 控制器被配置为执行从主机系统接收每个具有等于预定逻辑块大小的大小的一个或多个数据对象，并且将一个或多个数据对象存储在相应整数个存储器中的一个或多个存储器中 瓷砖。

    ECC Management for Variable Resistance Memory Cells
    29.
    发明申请
    ECC Management for Variable Resistance Memory Cells 有权
    可变电阻存储单元的ECC管理

    公开(公告)号：US20140245108A1

    公开(公告)日：2014-08-28

    申请号：US13779434

    申请日：2013-02-27

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Mark Allen Gaertner ,  Ryan James Goss ,  Antoine Khoueir ,  Ara Patapoutian

    IPC: G06F11/10

    CPC classification number: G06F11/1048 ,  G06F11/1008 ,  G06F11/1044 ,  G11C13/0002 ,  G11C17/165

    Abstract: A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.

    Abstract translation: 一般来说，数据存储设备可被构造和操作至少一个控制器，该控制器被配置为在至少一个可变电阻存储器单元中识别来自预定阈值的方差，并将第一纠错码（ECC）级别升级到第二ECC级别 至少一个可变电阻存储单元。

    Memory with separate read and write paths
    30.
    发明授权
    Memory with separate read and write paths 有权
    内存具有单独的读写路径

    公开(公告)号：US08711608B2

    公开(公告)日：2014-04-29

    申请号：US13785525

    申请日：2013-03-05

    Applicant: Seagate Technology LLC

    Inventor： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    IPC: G11C11/00

    CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

    Abstract translation: 存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。 巨磁电阻单元包括自由磁性层。 磁性隧道结数据单元电耦合在读取位线和读取源极线之间。 磁性隧道结数据单元包括自由磁性层。 写入电流通过巨磁电阻单元，以将巨磁阻单元切换到高电阻状态和低电阻状态之间。 磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

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