公开(公告)号：US09454923B2

公开(公告)日：2016-09-27

申请号：US14277248

申请日：2014-05-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hidetomo Kobayashi ,  Kiyoshi Kato ,  Wataru Uesugi

IPC: H03K17/687 ,  G09G3/00 ,  H03K19/00 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78

CPC classification number: G09G3/00 ,  G09G2330/022 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/7833 ,  H03K19/0016

Abstract: A semiconductor device with short overhead time. The semiconductor device includes a first wiring supplied with a power supply potential, a second wiring, a switch for controlling electrical connection between the first wiring and the second wiring, a load electrically connected to the second wiring, a transistor whose source and drain are electrically connected to the second wiring, and a power management unit having functions of controlling the conduction state of the switch and controlling a gate potential of the transistor. A channel formation region of the transistor is included in an oxide semiconductor film.

Abstract translation: 具有短占空时间的半导体器件。 所述半导体器件包括供给电源电位的第一布线，第二布线，用于控制所述第一布线和所述第二布线之间的电连接的开关，电连接到所述第二布线的负载，源极和漏极电连接的晶体管 连接到第二布线，以及功率管理单元，具有控制开关的导通状态和控制晶体管的栅极电位的功能。 晶体管的沟道形成区域包括在氧化物半导体膜中。

公开(公告)号：US20140203859A1

公开(公告)日：2014-07-24

申请号：US14160774

申请日：2014-01-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Wataru Uesugi

IPC: H03K5/04

CPC classification number: H03K5/06 ,  H03K5/05 ,  H03K2005/00104 ,  H03K2005/00241

Abstract: To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A first signal is input to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. A first clock signal is input to the circuit. The circuit outputs a second clock signal. The timing of the second clock signal is different from that of the first clock signal.

Abstract translation: 提供能够调整时钟信号或高质量半导体器件的定时的半导体器件。 半导体器件包括第一晶体管和包括第二晶体管的电路。 第一晶体管的沟道形成在氧化物半导体层中。 第一信号被输入到第一晶体管的源极和漏极之一。 第一晶体管的源极和漏极中的另一个电连接到第二晶体管的栅极。 第一时钟信号被输入到电路。 电路输出第二个时钟信号。 第二时钟信号的定时与第一时钟信号的定时不同。

公开(公告)号：US11374023B2

公开(公告)日：2022-06-28

申请号：US17083393

申请日：2020-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC: H03K19/173 ,  H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L29/04 ,  H01L29/78 ,  H03K19/00 ,  H03K19/0185 ,  G11C7/04

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US10296157B2

公开(公告)日：2019-05-21

申请号：US15161575

申请日：2016-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kei Takahashi ,  Wataru Uesugi ,  Hiromichi Godo

IPC: G02F1/1333 ,  G06F3/047 ,  G06F3/041 ,  G06F3/044 ,  H01L27/32

Abstract: To provide a display device which includes a touch sensor and a large number of pixels and in which a driver circuit of a display portion and a driver circuit of a touch sensor are formed in one IC. The display device includes the display portion, the touch sensor, and a plurality of ICs. The plurality of ICs each include a first circuit. One of the plurality of ICs includes a second circuit and a third circuit. The first circuit has a function of outputting a video signal to the display portion. The second circuit has a function of outputting a signal for driving a sensor element included in the touch sensor. The third circuit has a function of converting an analog signal output from the sensor element into a digital signal.

公开(公告)号：US10236884B2

公开(公告)日：2019-03-19

申请号：US15017879

申请日：2016-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Wataru Uesugi

IPC: G11C7/00 ,  H03K19/0175 ,  H03K19/00 ,  G11C8/08 ,  G11C11/412 ,  G11C29/50

Abstract: A semiconductor device with lower power consumption and an electronic device including the same are provided. To reduce leakage current flowing in a word line driver circuit, a switching element is provided, specifically, between the word line driver circuit and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the word line driver circuit. Furthermore, to reduce the stand-by power due to precharge of a bit line, a switching element is provided in a bit line driver circuit, specifically, between the bit line and a high or low voltage power source. When there is no memory access, the switching element is turned off, thereby interrupting application of voltage (or current) from the high or low voltage power source to the bit line driver circuit.

公开(公告)号：US09971680B2

公开(公告)日：2018-05-15

申请号：US14731940

申请日：2015-06-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Tomoaki Atsumi ,  Naoaki Tsutsui ,  Hikaru Tamura ,  Takahiko Ishizu ,  Takuro Ohmaru

IPC: G06F12/00 ,  G11C5/00 ,  H01L27/12 ,  H01L29/778 ,  H01L27/06 ,  H01L27/1156 ,  H01L29/24

CPC classification number: G06F12/00 ,  G11C5/00 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7782

Abstract: A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.

公开(公告)号：US09438206B2

公开(公告)日：2016-09-06

申请号：US14471322

申请日：2014-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yukio Maehashi ,  Seiichi Yoneda ,  Wataru Uesugi

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356 ,  H03K3/356104

Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.

Abstract translation: 存储电路包括第一和第二逻辑电路，其沟道形成区域包括氧化物半导体的第一和第二晶体管以及电容器。 第一和第二晶体管串联连接，电容器连接到第一和第二晶体管的连接节点。 第一晶体管用作控制第一逻辑电路的输出端子和电容器之间的连接的开关。 第二晶体管用作控制电容器和第二逻辑电路的输入端之间的连接的开关。 其相位相互反相的时钟信号被输入到第一和第二晶体管的栅极。 由于存储电路具有少量晶体管和由时钟信号控制的少量晶体管，所以存储电路是低功率电路。

公开(公告)号：US09300292B2

公开(公告)日：2016-03-29

申请号：US14591274

申请日：2015-01-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Yukio Maehashi

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/094 ,  H01L29/786 ,  H01L27/06

CPC classification number: H03K19/0013 ,  H01L27/0688 ,  H01L29/7869 ,  H01L29/78696 ,  H03K19/01855

Abstract: The power consumption of a semiconductor device that can function as a latch circuit or the like is reduced. The semiconductor device includes a first circuit and a switch that controls conduction between an input terminal and the first circuit. The first circuit includes n second circuits (n is an integer of 2 or more) and a variable resistor. An output node of any of the n second circuits is electrically connected to an input node of the second circuit in a first stage through the variable resistor. The variable resistor can be, for example, a transistor whose channel is formed in an oxide semiconductor layer. A reduction in the number of elements or signals leads to a reduction of the power consumption of the semiconductor device.

Abstract translation: 可以用作锁存电路等的半导体器件的功耗降低。 半导体器件包括第一电路和控制输入端和第一电路之间的导通的开关。 第一电路包括n个第二电路（n是2或更大的整数）和可变电阻器。 n个第二电路中的任一个的输出节点通过可变电阻器在第一级中电连接到第二电路的输入节点。 可变电阻器可以是例如其通道形成在氧化物半导体层中的晶体管。 元件或信号的数量的减少导致半导体器件的功耗的降低。

公开(公告)号：US09299432B2

公开(公告)日：2016-03-29

申请号：US13889957

申请日：2013-05-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Wataru Uesugi

IPC: G11C5/06 ,  G11C14/00 ,  G11C5/10

CPC classification number: G11C14/0054 ,  G11C5/063 ,  G11C5/10

Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

Abstract translation: 提供一种包括实现高速操作和较低功耗的易失性存储器的半导体器件。 例如，半导体器件包括设置有第一和第二数据保持部分的SRAM和设置有第三和第四第二数据保持部分的非易失性存储器。 第一数据保持部分通过晶体管与第四数据保持部分电连接。 第二数据保持部分通过晶体管与第三数据保持部分电连接。 当SRAM保存数据时，晶体管导通，以便SRAM和非易失性存储器都保存数据。 然后，在供电停止之前晶体管截止，使得数据变得非易失性。

公开(公告)号：US09294075B2

公开(公告)日：2016-03-22

申请号：US14199561

申请日：2014-03-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Wataru Uesugi

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/35606

Abstract: To provide a semiconductor device which can perform a scan test and includes a logic circuit capable of reducing signal delay. The semiconductor device includes a combinational circuit, sequential circuits each holding first data supplied to the combinational circuit or second data output from the combinational circuit, first memory circuits each holding first data supplied to the corresponding sequential circuit and holding second data output from the corresponding sequential circuit, and second memory circuits electrically connecting the first memory circuits in series by supplying the first data or second data supplied from one of the first memory circuits to another one of the first memory circuits. The second memory circuit includes a first switch controlling supply of the first data or second data to the node, a capacitor electrically connected to the node, and a second switch controlling output of the first data or second data from the node.

Abstract translation: 提供一种能够执行扫描测试并包括能够减少信号延迟的逻辑电路的半导体器件。 半导体器件包括组合电路，每个保持提供给组合电路的第一数据或从组合电路输出的第二数据的顺序电路，每个保持提供给相应的顺序电路的第一数据的第一存储器电路并且保持来自相应顺序的第二数据输出 电路和第二存储器电路通过将从第一存储器电路中的一个提供的第一数据或第二数据提供给第一存储器电路中的另一个而将第一存储器电路串联电连接。 第二存储电路包括控制向节点提供第一数据或第二数据的第一开关，电连接到该节点的电容器以及控制第一数据或第二数据从该节点输出的第二开关。