Active cooling to reduce leakage power
    23.
    发明申请
    Active cooling to reduce leakage power 有权
    主动冷却以减少漏电功率

    公开(公告)号:US20050052196A1

    公开(公告)日:2005-03-10

    申请号:US10972838

    申请日:2004-10-22

    申请人: Shekhar Borkar

    发明人: Shekhar Borkar

    摘要: Leakage power consumed by an integrated circuit is estimated as the difference between total power consumption and a nominal expected power consumption. Leakage power is reduced by cooling the integrated circuit in an active cooling system. By expending power in the active cooling system, the integrated circuit is cooled and the total power consumption is decreased. When the decrease in total power consumption is greater than the power expended in the cooling system, an overall power savings is achieved.

    摘要翻译: 集成电路消耗的泄漏功率被估计为总功耗与标称预期功耗之间的差异。 通过在主动冷却系统中冷却集成电路来降低泄漏功率。 通过在主动冷却系统中消耗功率,集成电路被冷却,总功耗降低。 当总功耗的降低大于冷却系统中消耗的功率时,可实现总体功率节省。

    Temperature, voltage, and process compensated output driver
    24.
    发明授权
    Temperature, voltage, and process compensated output driver 失效
    温度,电压和过程补偿输出驱动器

    公开(公告)号:US4975598A

    公开(公告)日:1990-12-04

    申请号:US287915

    申请日:1988-12-21

    申请人: Shekhar Borkar

    发明人: Shekhar Borkar

    IPC分类号: H03K19/003 H03K19/0185

    摘要: An output driver for high performance integrated circuits. The driver dynamically compensates for variations in temperature, voltage and process. To perform the compensation, the driver is divided into two parts: static and transient. The static part is used to maintain the DC level. The transient part is active only during logic 0 to 1 and 1 to 0 transitions and is used only to assist the static part during such transitions. A closed loop feedback technique is used to compensate the driver for temperature, process, and voltage variations; specifically, a scaled down version of an output driver is used to monitor speed variations due to temperature, process, and voltage, the output of which is fed back to the output driver which then performs the necessary compensation.

    摘要翻译: 用于高性能集成电路的输出驱动器。 驱动程序动态补偿温度,电压和过程的变化。 为了执行补偿,驱动程序分为静态和瞬态两部分。 静态部分用于维持直流电平。 瞬态部分仅在逻辑0至1和1至0转换期间有效,仅用于在此过渡期间辅助静态部分。 闭环反馈技术用于补偿驱动器的温度,过程和电压变化; 特别地,输出驱动器的缩小版本用于监视由于温度,过程和电压引起的速度变化,其输出被反馈到输出驱动器,然后执行必要的补偿。

    Reliable computing with a many-core processor
    26.
    发明申请
    Reliable computing with a many-core processor 有权
    可靠的计算与多核处理器

    公开(公告)号:US20070074011A1

    公开(公告)日:2007-03-29

    申请号:US11238488

    申请日:2005-09-28

    IPC分类号: G06F15/00

    摘要: According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as the trending information of these parameters. Once a dynamic profile has been created for each core, cores in a many-core processor may be grouped into different bins according to their characteristics. Based on dynamic profiles and the grouping information, the operating system (“OS”) or other software may allocate a task to those cores that are most suitable for the task. The interconnect fabric in the many-core processor may be reconfigured to ensure a high level of connectivity among the selected cores. Additionally, cores may be re-allocated and/or re-balanced to a task in response to changes in the environment.

    摘要翻译: 根据所公开的主题的实施例,可以定期测试多核处理器中的核心以获得和/或刷新其动态简档。 核心的动态分布可以包括关于其最大工作频率,功耗,功率泄漏,功能正确性和其他参数的信息以及这些参数的趋势信息。 一旦为每个核心创建了动态配置文件,多核处理器中的核心可以根据其特征被分组到不同的箱中。 基于动态配置文件和分组信息,操作系统(“OS”)或其他软件可以将任务分配给最适合任务的那些核心。 可以重新配置多核处理器中的互连结构,以确保所选核心之间的高水平连接。 此外,响应于环境变化,核可以被重新分配和/或重新平衡到任务。

    Power delivery and power management of many-core processors
    27.
    发明申请
    Power delivery and power management of many-core processors 有权
    多核处理器的供电和电源管理

    公开(公告)号:US20070070673A1

    公开(公告)日:2007-03-29

    申请号:US11238489

    申请日:2005-09-28

    IPC分类号: G11C5/06

    摘要: According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.

    摘要翻译: 根据本申请中公开的主题的实施例,具有多个电压调节器(“VR”)的电力管理系统可以用于向多核处理器中的核供电。 每个VR可以为核心或核心的一部分供电。 不同的VR可以为多核处理器中的核/部件提供多个电压。 VR的输出电压的值可以在电压调节器供电的核心/部件的方向上进行调制。 在一个实施例中,多个VR可以与单个管芯中的核心集成。 在另一个实施例中,具有多个VR的电源管理系统可以在与多核处理器的管芯分开的管芯(“VR管芯”)上。 VR芯片可以包含在与多核处理器芯片相同的封装中。

    Systems for interchip communication
    28.
    发明申请
    Systems for interchip communication 审中-公开
    芯片间通信系统

    公开(公告)号:US20060110952A1

    公开(公告)日:2006-05-25

    申请号:US10995851

    申请日:2004-11-22

    IPC分类号: H05K1/00

    CPC分类号: G06F13/4086

    摘要: In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.

    摘要翻译: 在一些实施例中,本发明涉及具有以截头环方式连接的第一组集成电路的系统,其中所述截头环包括截取的区域,以允许将额外的集成电路添加到所述环中。 在一些实施例中,本发明涉及具有以伪环方式连接的一组集成电路的系统,其中通过集成电路之间的双向信令的数据流创建伪环。 在一些实施例中,本发明涉及一种具有以伪差分布置连接的一组集成电路的系统,其中携带多个导体的信号共用公共参考信号导体。

    High speed bidirectional signaling scheme
    30.
    发明授权
    High speed bidirectional signaling scheme 失效
    高速双向信令方案

    公开(公告)号:US5604450A

    公开(公告)日:1997-02-18

    申请号:US508159

    申请日:1995-07-27

    CPC分类号: H03K19/01759 H03K5/026

    摘要: In a computer system having multiple components, a bidirectional scheme which allows bidirectional data communications between components over a single wire without using termination resistors by placing two drivers from two corresponding processor cores on the same wire, and allowing simultaneous data transfer in two directions. This doubles the effective bandwidth per pin without requiring a modification to the clocking scheme of the system. The driver is impedance matched to the line, and used as the termination for the driver on the opposite end of the wire. This reduces the termination power, since no power is consumed when both drivers are in the same state. The bidirectional flow of data creates a ternary encoding, with a relatively simple decoding possible.

    摘要翻译: 在具有多个组件的计算机系统中,双向方案允许通过单个线路在组件之间进行双向数据通信而不使用终端电阻器,通过将来自两个对应的处理器核心的两个驱动器放置在相同的线路上,并允许在两个方向上同时进行数据传输。 这可以使每个引脚的有效带宽增加一倍,而不需要修改系统的时钟方案。 驱动器与线路阻抗匹配,并用作线缆另一端的驱动器终端。 这降低了终端功率,因为​​当两个驱动器处于相同状态时都不消耗电力。 数据的双向流创建三进制编码,可以使用相对简单的解码。