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    Data storing method of dynamic RAM and semiconductor memory device
    21.
    发明授权
    Data storing method of dynamic RAM and semiconductor memory device 有权
    动态RAM和半导体存储器件的数据存储方法

    公开(公告)号：US06697992B2

    公开(公告)日：2004-02-24

    申请号：US09923405

    申请日：2001-08-08

    申请人： Yutaka Ito ,  Hidetoshi Iwai

    发明人： Yutaka Ito ,  Hidetoshi Iwai

    IPC分类号： G11C2900

    CPC分类号： G06F11/1008 ,  G06F11/106 ,  G06F11/108 ,  G11C7/1006 ,  G11C7/1045 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4062

    摘要： When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

    摘要翻译： 当DRAM进入仅执行数据存储操作的操作模式时，生成并存储用于多个数据的错误检测和校正的校验位。 在通过使用校验位的纠错操作的错误发生的允许范围内的更新周期中执行刷新操作。 在DRAM从数据保持操作模式返回到正常操作模式之前，通过使用数据和校验位来校正错误位。

    Semiconductor integrated circuit device
    22.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5654577A

    公开(公告)日：1997-08-05

    申请号：US476761

    申请日：1995-06-07

    申请人： Masayuki Nakamura ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai

    发明人： Masayuki Nakamura ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai

    IPC分类号： H01L27/04 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L27/105

    摘要： A semiconductor integrated circuit device includes in a substrate a P-type well region containing a memory array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage. Accordingly, the P-type well region provided with the input circuit or the output circuit corresponding to the external terminals is fed with the back bias voltage to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit can be raised.

    摘要翻译： 半导体集成电路器件在衬底中包括含有存储器阵列部分的P型阱区域，其中动态存储器单元被布置成矩阵。 P型阱区域馈送有绝对值减小的背偏置电压，以便最适合刷新特性。 还包括P阱区，其中形成外围电路的N沟道MOSFET，该P阱区被馈送反馈偏压，其绝对值小于馈送到P型阱的电位的绝对值 存储器阵列部分，考虑高速运行。 其中形成有输入电路的N沟道MOSFET或与外部端子连接的输出电路的P型阱区，考虑到下冲电压，馈送绝对值较大的反向偏置电压。 设置有存储器阵列部分的P型阱区域被馈送必需的最小反向偏置电压。 因此，设置有与外部端子相对应的输入电路或输出电路的P型阱区域被馈送有反向偏置电压，以提供对下冲的保护措施，同时通过减小刷新特性来减小 可以提高与电容器和P型阱连接的源极/漏极区域，从而提高外围电路的操作速度。

    Semiconductor integrated circuit device having input protective elements and internal circuits
    23.
    发明授权
    Semiconductor integrated circuit device having input protective elements and internal circuits 失效
    具有输入保护元件和内部电路的半导体集成电路器件

    公开(公告)号：US5436484A

    公开(公告)日：1995-07-25

    申请号：US143151

    申请日：1993-10-29

    申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

    CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

    摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

    摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

    Semiconductor integrated circuit device having protective/output elements and internal circuits
    25.
    发明授权
    Semiconductor integrated circuit device having protective/output elements and internal circuits 失效
    具有保护/输出元件和内部电路的半导体集成电路器件

    公开(公告)号：US5276346A

    公开(公告)日：1994-01-04

    申请号：US815863

    申请日：1992-01-02

    申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

    CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

    摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatoc protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

    摘要翻译： 本发明公开了一种半导体器件，其具有由静电场保护电路保护的内部电路，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一个实施例，提供一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

    Semiconductor memory device
    26.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20050286330A1

    公开(公告)日：2005-12-29

    申请号：US11154467

    申请日：2005-06-17

    申请人： Yutaka Ito ,  Eiji Yamasaki ,  Hidetoshi Iwai

    发明人： Yutaka Ito ,  Eiji Yamasaki ,  Hidetoshi Iwai

    IPC分类号： G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G11C2211/4062

    摘要： Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried out at a time of an exit from the data retention operating mode, by an ECC (Error Correction Circuit). The semiconductor memory device includes means for outputting from an NC pin flag information indicating that the semiconductor memory device is the one including the data retention operating mode, that the exit processing from the data retention operating mode is under way, and that the error correction cannot be performed.

    摘要翻译： 公开了具有数据保持操作模式的半导体存储器件。 当执行进入数据保持操作模式的进入时，计算存储器单元的数据的奇偶校验信息，并且在从数据保留操作模式退出时，通过ECC执行对存储器单元的错误校正（ 纠错电路）。 半导体存储装置包括用于从NC引脚标志输出指示半导体存储器件是包括数据保持操作模式的信息的装置，即数据保持操作模式的退出处理正在进行，并且纠错不能 被执行。

    Semiconductor integrated circuit device
    27.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06906971B2

    公开(公告)日：2005-06-14

    申请号：US10767078

    申请日：2004-01-30

    申请人： Masayuki Nakamura ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai

    发明人： Masayuki Nakamura ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai

    IPC分类号： H01L27/04 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  G11C7/00

    CPC分类号： H01L27/105

    摘要： A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.

    摘要翻译： 半导体IC器件在衬底中包括具有动态存储器阵列部分并且施加有适于刷新的减小的背偏压的P型阱区。 还包括形成外围电路的N沟道MOSFET的P阱区。 该P阱区域施加的绝对值的反偏压小于施加到存储器阵列部分的P型阱的绝对值。 形成输入电路的N沟道MOSFET或与外部端子连接的输出电路的P型阱部分被施加绝对值足够大的背偏压以提供防止下冲的保护措施， 同时通过减少与电容器连接的源极/漏极区域与P型阱之间的漏电流来改善刷新特性，从而提高外围电路的操作速度。

    Semiconductor device
    28.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06680501B2

    公开(公告)日：2004-01-20

    申请号：US10091488

    申请日：2002-03-07

    申请人： Yutaka Ito ,  Hidetoshi Iwai

    发明人： Yutaka Ito ,  Hidetoshi Iwai

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

    摘要： A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line consisting of different layers in the row direction with an identical pitch, and, also, alternately arranging the first word line and the second word line at an interval equal to a half of the pitch in the horizontal direction. Moreover, the selection MISFET of the memory cell is formed to have the vertical construction and the bit line located at the upper side of the substrate, where a channel region is formed, is shielded with a conductive film, a part of which forms the gate electrode.

    摘要翻译： 存储单元被布置在第一字线和位线对的一行的所有交点处，并且通过并行排列第一字线和第二字线，布置第二字线和位线对的另一行的所有交点 第二字线由具有相同节距的行方向上的不同层组成，并且还以等于水平方向上的间距的一半的间隔交替地布置第一字线和第二字线。 此外，存储单元的选择MISFET被形成为具有垂直结构，并且位于形成沟道区的衬底的上侧的位线被导电膜屏蔽，其中一部分形成栅极 电极。

    Semiconductor integrated circuit device
    29.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US6078084A

    公开(公告)日：2000-06-20

    申请号：US823167

    申请日：1997-03-25

    申请人： Masayuki Nakamura ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai

    发明人： Masayuki Nakamura ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai

    IPC分类号： H01L27/04 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

    CPC分类号： H01L27/105

    摘要： A semiconductor integrated circuit device includes in a P-type well region containing a memory substrate a array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage. Accordingly, the P-type well region provided with the input circuit or the output circuit corresponding to the external terminals is fed with the back bias voltage to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit can be raised.

    摘要翻译： 半导体集成电路器件包括在包含存储器基板的P型阱区中，其中动态存储单元以矩阵形式布置在其中。 P型阱区域馈送有绝对值减小的背偏置电压，以便最适合刷新特性。 还包括P阱区，其中形成外围电路的N沟道MOSFET，该P阱区被馈送反馈偏压，其绝对值小于馈送到P型阱的电位的绝对值 存储器阵列部分，考虑高速运行。 其中形成有输入电路的N沟道MOSFET或与外部端子连接的输出电路的P型阱区，考虑到下冲电压，馈送绝对值较大的反向偏置电压。 设置有存储器阵列部分的P型阱区域被馈送必需的最小反向偏置电压。 因此，设置有与外部端子相对应的输入电路或输出电路的P型阱区域被馈送有反向偏置电压，以提供对下冲的保护措施，同时通过减小刷新特性来减小 可以提高与电容器和P型阱连接的源极/漏极区域，从而提高外围电路的操作速度。