摘要:
A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要:
Apparatus and systems, as well as methods and articles, may operate to select a microprocessor clock frequency responsive to a desired voltage and/or a desired temperature of operation.
摘要:
In some embodiments, a method includes providing an integrated circuit (IC) die in a package. The IC die may have a metal layer on a back surface of the IC die. The method may also include applying a bias signal to the IC die via the metal layer.
摘要:
A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要:
A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要:
A logic unit and method incorporating body biasing using scan chains, the logic unit comprising a functional unit block including a body and a scan chain, and a variable voltage source coupled to the scan chain to receive control signals from the scan chain and coupled to the body to provide a bias voltage to the body, and the method comprising identifying a preferred body bias voltage for a functional unit block having a body; and permanently programming a plurality of control signals coupled to a variable voltage source that provides the preferred body bias voltage to the body.
摘要:
A current reference, which may be fabricated independently, on a die, as part of an integrated circuit, or a system, or in various other forms, is disclosed. The current reference may include a voltage source having a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device providing a second output current, wherein a reference current is provided approximately equal to the difference between the first and second output currents.
摘要:
A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.
摘要:
In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.
摘要:
One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.