公开(公告)号：US08994104B2

公开(公告)日：2015-03-31

申请号：US13990224

申请日：2011-09-30

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L29/36 ,  G11C7/10 ,  G11C16/04 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  H01L21/285 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  G11C16/08 ,  H01L21/768

CPC分类号： H01L29/36 ,  G11C7/1051 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2216/14 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76814 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

摘要翻译： 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 这些技术可以例如使用例如硅或硅锗（SiGe）源极/漏极区域上的一系列金属的标准接触堆叠来实现。 根据这种实施例的一个示例，在源极/漏极和接触金属之间提供中间硼掺杂锗层以显着降低接触电阻。 根据本公开，包括平面和非平面晶体管结构（例如，FinFET）以及应变和非限制的通道结构，许多晶体管配置和合适的制造工艺将是显而易见的。 分级缓冲可用于减少错配错位。 这些技术特别适用于实现p型器件，但如果需要，可以用于n型器件。

公开(公告)号：US20130240989A1

公开(公告)日：2013-09-19

申请号：US13990238

申请日：2011-09-30

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L29/167

CPC分类号： H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

公开(公告)号：US09117791B2

公开(公告)日：2015-08-25

申请号：US13990238

申请日：2011-09-30

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L31/00 ,  H01L21/02 ,  H01L29/36 ,  H01L21/285 ,  H01L29/165 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L29/08

CPC分类号： H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

摘要翻译： 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 这些技术可以例如使用例如硅或硅锗（SiGe）源极/漏极区域上的一系列金属的标准接触堆叠来实现。 根据这种实施例的一个示例，在源极/漏极和接触金属之间提供中间硼掺杂锗层以显着降低接触电阻。 根据本公开，包括平面和非平面晶体管结构（例如，FinFET）以及应变和非限制的通道结构，许多晶体管配置和合适的制造工艺将是显而易见的。 分级缓冲可用于减少错配错位。 这些技术特别适用于实现p型器件，但如果需要，可以用于n型器件。

公开(公告)号：US09153583B2

公开(公告)日：2015-10-06

申请号：US13976074

申请日：2011-12-20

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/78618 ,  H01L21/76805 ,  H01L21/76886 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

摘要翻译： 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 在一些示例性实施例中，该技术可以用于实现CMOS器件的MOS晶体管的触点，其中在p型和n型源极/漏极区之间提供中间III-V半导体材料层及其各自的触点 金属显着降低接触电阻。 中间III-V半导体材料层可以具有小的带隙（例如，低于0.5eV）和/或以其它方式被掺杂以提供期望的导电性。 这些技术可以用于许多晶体管架构（例如，平面，鳍状和纳米线晶体管），包括应变和无约束通道结构。

公开(公告)号：US09059024B2

公开(公告)日：2015-06-16

申请号：US13976075

申请日：2011-12-20

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L21/8258 ,  H01L27/06 ,  H01L21/285 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L21/768

CPC分类号： H01L27/0922 ,  H01L21/28185 ,  H01L21/28525 ,  H01L21/28575 ,  H01L21/76814 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g.,

摘要翻译： 公开了用于形成低接触电阻晶体管器件的技术。 p型锗层设置在p型源极/漏极区及其各自的接触金属之间，n型III-V半导体材料层设置在n型源极/漏极区及其各自的接触金属之间。 n型III-V族半导体材料层可以具有小的带隙（例如，<0.5eV）和/或以其它方式掺杂以提供期望的导电性，并且p型锗层可以例如用硼掺杂。 在III型V材料沉积在n型源极/漏极区域和锗覆盖的p型源极/漏极区域之后，可以执行回蚀工艺以利用n型和p型之间的高度差 区域自对准接触类型，并在p型区域上露出p型锗，并在n型区域上稀薄n型III-V材料。 这些技术可以用于平面和非平面晶体管架构。

公开(公告)号：US07833883B2

公开(公告)日：2010-11-16

申请号：US11692782

申请日：2007-03-28

申请人： Danielle M. Simonelli ,  Anand S. Murthy ,  Daniel B. Aubertine

发明人： Danielle M. Simonelli ,  Anand S. Murthy ,  Daniel B. Aubertine

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L29/7834 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L29/66636 ,  H01L29/7848

摘要： A precursor gas mixture for depositing an epitaxial carbon-doped silicon film is described. The precursor gas mixture is comprised of a volume of a silicon precursor gas, a volume of acetylene gas and a volume of a carrier gas. A method of forming a semiconductor structure having an epitaxial carbon-doped silicon film is also described. In the method, a substrate having a high polarity dielectric region and a low polarity crystalline region is provided. A precursor gas is flowed to provide a silyl surface above the high polarity dielectric region and a carbon-doped silicon layer above the low polarity crystalline region. The silyl surface is then removed from above the high polarity dielectric region. The flowing and removing steps are repeated to provide a carbon-doped silicon film of a desired thickness above the low polarity crystalline region.

摘要翻译： 描述了用于沉积外延碳掺杂硅膜的前体气体混合物。 前体气体混合物由体积的硅前体气体，一定体积的乙炔气体和一定体积的载气构成。 还描述了形成具有外延碳掺杂硅膜的半导体结构的方法。 在该方法中，提供具有高极性电介质区域和低极性结晶区域的衬底。 流动前体气体以在高极性电介质区域上方提供甲硅烷基表面，以及在低极性结晶区域上方的碳掺杂硅层。 然后从高极性介电区域上方除去甲硅烷基表面。 重复流动和去除步骤以提供在低极性结晶区域之上所需厚度的碳掺杂硅膜。

公开(公告)号：US20080242061A1

公开(公告)日：2008-10-02

申请号：US11692782

申请日：2007-03-28

申请人： Danielle M. Simonelli ,  Anand S. Murthy ,  Daniel B. Aubertine

发明人： Danielle M. Simonelli ,  Anand S. Murthy ,  Daniel B. Aubertine

IPC分类号： H01L21/20 ,  C09K13/04

CPC分类号： H01L29/7834 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L29/66636 ,  H01L29/7848

摘要： A precursor gas mixture for depositing an epitaxial carbon-doped silicon film is described. The precursor gas mixture is comprised of a volume of a silicon precursor gas, a volume of acetylene gas and a volume of a carrier gas. A method of forming a semiconductor structure having an epitaxial carbon-doped silicon film is also described. In the method, a substrate having a high polarity dielectric region and a low polarity crystalline region is provided. A precursor gas is flowed to provide a silyl surface above the high polarity dielectric region and a carbon-doped silicon layer above the low polarity crystalline region. The silyl surface is then removed from above the high polarity dielectric region. The flowing and removing steps are repeated to provide a carbon-doped silicon film of a desired thickness above the low polarity crystalline region.

摘要翻译： 描述了用于沉积外延碳掺杂硅膜的前体气体混合物。 前体气体混合物由体积的硅前体气体，一定体积的乙炔气体和一定体积的载气构成。 还描述了形成具有外延碳掺杂硅膜的半导体结构的方法。 在该方法中，提供具有高极性电介质区域和低极性结晶区域的衬底。 流动前体气体以在高极性电介质区域上方提供甲硅烷基表面，以及在低极性结晶区域上方的碳掺杂硅层。 然后从高极性介电区域上方除去甲硅烷基表面。 重复流动和去除步骤以提供在低极性结晶区域之上所需厚度的碳掺杂硅膜。

公开(公告)号：US20110147842A1

公开(公告)日：2011-06-23

申请号：US12646518

申请日：2009-12-23

申请人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

发明人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/3065 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (Hsi), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hsi proximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.

摘要翻译： 具有低寄生电阻的通道应变多栅极晶体管及其制造方法。 可以在具有栅极耦合侧壁高度（Hsi）的半导体鳍片上形成栅极堆叠，蚀刻速率控制掺杂剂可以注入到与栅极堆叠相邻的半导体鳍片的源极/漏极区域中并且被注入到源极/漏极 半导体鳍片的延伸区域。 可以蚀刻掺杂散热片区域以除去等于沟道区域附近的至少Hsi的半导体鳍片的厚度并形成源极/漏极延伸底切。 可以在暴露的半导体衬底上生长材料以形成填充源极/漏极延伸底切区域的再生长源极/漏极鳍区域。

公开(公告)号：US20110147828A1

公开(公告)日：2011-06-23

申请号：US12643912

申请日：2009-12-21

申请人： Anand S. Murthy ,  Daniel Bourne Aubertine ,  Tahir Ghani ,  Abhijit Javant Pethe

发明人： Anand S. Murthy ,  Daniel Bourne Aubertine ,  Tahir Ghani ,  Abhijit Javant Pethe

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28079 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

摘要： Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

摘要翻译： 本发明的实施例描述了半导体器件上的外延区域。 在一个实施例中，通过循环沉积蚀刻工艺将外延区域沉积到衬底上。 在循环沉积 - 蚀刻工艺期间在间隔物下方产生的腔被外延盖层回填。 外延区和外延盖层改善沟道区的电子迁移率，减少短沟道效应并降低寄生电阻。

公开(公告)号：US20230197838A1

公开(公告)日：2023-06-22

申请号：US17558046

申请日：2021-12-21

申请人： Mohammad HASAN ,  Leonard P. GULER ,  Anand S. Murthy ,  Pratik PATEL ,  Tahir GHANI

发明人： Mohammad HASAN ,  Leonard P. GULER ,  Anand S. Murthy ,  Pratik PATEL ,  Tahir GHANI

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

摘要： Gate-all-around integrated circuit structures having source or drain-last structures, and methods of fabricating gate-all-around integrated circuit structures having source or drain-last structures, are described. For example, a method of fabricating an integrated circuit structure includes forming a vertical arrangement of nanowires. A permanent gate stack is then formed over the vertical arrangements of nanowires. The permanent gate stack includes a high-k gate dielectric layer and a metal gate electrode. Subsequent to forming the permanent gate stack, a first epitaxial source or drain structure is formed at a first end of the vertical arrangement of nanowires, and a second epitaxial source or drain structure is formed at a second end of the vertical arrangement of nanowires.