公开(公告)号：US20130320483A1

公开(公告)日：2013-12-05

申请号：US13483781

申请日：2012-05-30

申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/762 ,  H01L29/02

CPC分类号： H01L21/76243

摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

公开(公告)号：US07749869B2

公开(公告)日：2010-07-06

申请号：US12186243

申请日：2008-08-05

申请人： Joel P. De Souza ,  Harold John Hovel ,  Daniel A. Inns ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Joel P. De Souza ,  Harold John Hovel ,  Daniel A. Inns ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/322 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3225 ,  H01L21/02032

摘要： A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.

摘要翻译： 描述了一种用于改善其中具有金属污染物的含硅晶片的少数寿命的方法，其包括在1200℃或更高温度下退火并提供氧气，惰性气体和含氯气体如HCl的气态环境。

公开(公告)号：US20100035409A1

公开(公告)日：2010-02-11

申请号：US12186243

申请日：2008-08-05

申请人： Joel P De Souza ,  Harold John Hovel ,  Daniel A. Inns ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Joel P De Souza ,  Harold John Hovel ,  Daniel A. Inns ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/322

CPC分类号： H01L21/3225 ,  H01L21/02032

摘要： A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.

摘要翻译： 描述了一种用于改善其中具有金属污染物的含硅晶片的少数寿命的方法，其包括在1200℃或更高温度下退火并提供氧气，惰性气体和含氯气体如HCl的气态环境。

公开(公告)号：US07317226B2

公开(公告)日：2008-01-08

申请号：US10993270

申请日：2004-11-19

申请人： Keith E. Fogel ,  Mark C. Hakey ,  Steven J. Holmes ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Keith E. Fogel ,  Mark C. Hakey ,  Steven J. Holmes ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/01

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 μm or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein the patterned dielectric mask includes vertical edges that define boundaries for at least one opening which exposes a portion of the Si-containing substrate; implanting oxygen ions through the at least one opening removing the mask and forming a Si layer on at least the exposed surfaces of the Si-containing substrate; and annealing at a temperature of about 1250° C. or above and in an oxidizing ambient so as to form at least one discrete buried oxide region in the Si-containing substrate. In one embodiment, the mask is not removed until after the annealing step; and in another embodiment, the Si-containing layer is formed after annealing and mask removal.

摘要翻译： 提供了在含Si衬底中形成图案化SOI区的方法，其具有约0.25μm或更小的几何形状。 具体而言，一种方法包括以下步骤：在含Si衬底的表面上形成图案化电介质掩模，其中，图案化电介质掩模包括垂直边缘，其限定至少一个露出一部分含Si衬底的开口的边界 ; 通过所述至少一个开口注入氧离子，去除所述掩模并在至少所述含Si衬底的暴露表面上形成Si层; 并在约1250℃或更高的温度下和在氧化环境中进行退火，以便在含Si衬底中形成至少一个离散的掩埋氧化物区域。 在一个实施例中，直到退火步骤之后，掩模才被去除; 并且在另一个实施方案中，在退火和掩模去除之后形成含Si层。

公开(公告)号：US08866227B2

公开(公告)日：2014-10-21

申请号：US13607743

申请日：2012-09-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/77 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

公开(公告)号：US20130099319A1

公开(公告)日：2013-04-25

申请号：US13607743

申请日：2012-09-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

公开(公告)号：US20130099318A1

公开(公告)日：2013-04-25

申请号：US13280850

申请日：2011-10-25

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/092 ,  H01L21/20

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

公开(公告)号：US20110175166A1

公开(公告)日：2011-07-21

申请号：US12689339

申请日：2010-01-19

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/7849

摘要： A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.

摘要翻译： 半导体器件和制造方法包括在一个轴上具有应变的应变半导体层。 在半导体层中形成长鳍片和短鳍片，使得长鳍片沿着一个轴线具有应变长度。 在长鳍片上形成n型晶体管，在该至少一个短鳍片上形成p型晶体管。 n型晶体管中的应变提高了性能。

公开(公告)号：US20140048122A1

公开(公告)日：2014-02-20

申请号：US13586138

申请日：2012-08-15

申请人： Keith E. Fogel ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Keith E. Fogel ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/105 ,  H01L31/18

CPC分类号： H01L31/078 ,  H01L31/035227 ,  H01L31/035281 ,  H01L31/0725 ,  H01L31/0745 ,  H01L31/076 ,  H01L31/1824 ,  H01L31/1884 ,  H01L31/20 ,  Y02E10/548

摘要： A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.

摘要翻译： 一种光电器件，其包括吸收光的第一波长范围的上电池和吸收第二波长波长的底电池。 底部电池包括含有结晶含锗（Ge）层的异质结。 含结晶锗（Ge）层的至少一个表面与含有结晶（Ge）层的带隙较大的含硅（Si）层接触。

公开(公告)号：US06800518B2

公开(公告)日：2004-10-05

申请号：US10334220

申请日：2002-12-30

申请人： Robert E. Bendernagel ,  Kwang Su Choe ,  Bijan Davari ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

发明人： Robert E. Bendernagel ,  Kwang Su Choe ,  Bijan Davari ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC分类号： H01L318234

CPC分类号： H01L21/324 ,  H01L21/76243

摘要： A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structure are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.

摘要翻译： 提供了图案化的SOI / SON复合结构及其形成方法。 在SOI / SON复合结构中，图案化SOI / SON结构夹在Si上层和半导体衬底之间。 形成图案化SOI / SON复合结构的方法包括共同的处理步骤，其中SOI和SON结构形成在一起。 本发明还提供一种形成复合结构的方法，该复合结构包括掩埋导电/ SON结构以及形成仅包括掩埋空隙平面的复合结构的方法。