公开(公告)号：US20150001606A1

公开(公告)日：2015-01-01

申请号：US13929924

申请日：2013-06-28

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L29/49 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28518 ,  H01L27/105 ,  H01L27/11536 ,  H01L29/42332 ,  H01L29/45 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7882

摘要： A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

摘要翻译： 使用衬底形成分离栅极存储单元结构的方法包括形成包括选择栅极和覆盖在选择栅极上的电介质部分的栅极堆叠。 电荷存储层形成在包括在栅叠层上的衬底上。 导电材料的第一侧壁间隔物沿着延伸经过选择栅极的顶部的栅极堆叠的第一侧壁形成。 电介质材料的第二侧壁间隔物沿着第一侧壁间隔件上的第一侧壁形成。 使用第二侧壁间隔物作为掩模使第一侧壁间隔物的一部分硅化，由此硅化物不延伸到电荷存储层。

公开(公告)号：US09252246B2

公开(公告)日：2016-02-02

申请号：US13972372

申请日：2013-08-21

申请人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

发明人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42332

摘要： A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

摘要翻译： 制造半导体结构的方法包括在NVM区域中形成选择栅极和电荷存储层。 通过沉积保形层，接着进行回蚀而形成控制栅极。 图案化的蚀刻导致将电荷存储层的一部分留在选择栅极上并在控制栅极之下并且从逻辑区域去除电荷存储层。 形成在逻辑区域中的逻辑门结构具有被绝缘层包围的金属功函数。

公开(公告)号：US08530950B1

公开(公告)日：2013-09-10

申请号：US13485873

申请日：2012-05-31

申请人： Sung-Taeg Kang ,  Cheong Min Hong

发明人： Sung-Taeg Kang ,  Cheong Min Hong

IPC分类号： H01L29/76

CPC分类号： H01L29/42328 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： A split gate memory cell comprising a substrate including semiconductor material and a first gate structure of the memory cell located over the substrate. The first gate structure includes a first side wall having a lower portion and an upper portion. The upper portion is inset from the lower portion. A charge storage structure of the memory cell is located laterally to the first side wall. A second gate structure is located over the substrate and over at least a portion of the charge storage structure. The second gate structure is located laterally to the first gate structure such that the first side wall is located between the first gate structure and the second gate structure. A dielectric structure located against the upper portion of the first side wall and has a portion located over the lower portion of the first side wall.

摘要翻译： 一种分离栅极存储单元，包括包括半导体材料的衬底和位于衬底上方的存储单元的第一栅极结构。 第一栅极结构包括具有下部和上部的第一侧壁。 上部从下部插入。 存储单元的电荷存储结构位于第一侧壁的横向。 第二栅极结构位于衬底上并且在电荷存储结构的至少一部分上方。 第二栅极结构位于第一栅极结构的侧面，使得第一侧壁位于第一栅极结构和第二栅极结构之间。 电介质结构，位于第一侧壁的上部并且具有位于第一侧壁下部的部分。

公开(公告)号：US07871886B2

公开(公告)日：2011-01-18

申请号：US12436558

申请日：2009-05-06

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02601 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.

摘要翻译： 使用半导体衬底制造半导体器件的方法包括在半导体衬底上形成具有第一带能的第一绝缘层。 具有第二带能的第一半导体层形成在第一绝缘层上。 第一半导体层被退火以从第一半导体层形成多个第一电荷保持器球。 在多个第一电荷保持器球的每个电荷保持器球上形成第一保护膜。 在多个第一电荷保持器球上形成具有第三带能的第二半导体层。 第二半导体层被退火以在多个第一电荷保持器球上从第二半导体层形成多个存储小球。 第二带能量的大小在第一带能量的大小和第三带能量的大小之间。

公开(公告)号：US09514945B2

公开(公告)日：2016-12-06

申请号：US14568155

申请日：2014-12-12

申请人： Cheong Min Hong ,  Euhngi Lee

发明人： Cheong Min Hong ,  Euhngi Lee

IPC分类号： H01L21/28 ,  H01L27/115

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L27/11517 ,  H01L27/11563 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides. The deuterated hydride can be used to form an amorphous semiconductor material that is annealed to form nanoparticles to be incorporated into the charge-storing layer.

摘要翻译： 电荷存储装置包括具有纳米晶体的电荷存储层。 纳米晶体通过结合氘代氢化物的沉积技术形成。 氘代氢化物可用于形成非晶半导体材料，其被退火以形成要并入电荷存储层的纳米颗粒。

公开(公告)号：US09397176B2

公开(公告)日：2016-07-19

申请号：US14446796

申请日：2014-07-30

申请人： Cheong Min Hong ,  Konstantin V. Loiko ,  Jane A. Yater

发明人： Cheong Min Hong ,  Konstantin V. Loiko ,  Jane A. Yater

IPC分类号： H01L21/8239 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/08 ,  H01L29/41

CPC分类号： H01L29/42328 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

摘要： A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.

摘要翻译： 第一掺杂区从衬底的顶表面延伸到第一深度。 植入第一掺杂区域形成第二导电类型的第二掺杂区域。 第二掺杂区从顶表面延伸到小于第一深度的第二深度。 分裂门NVM结构在第二掺杂区域上具有选择和控制栅极。 形成与选择栅极相邻的第二导电类型的漏极区域。 第二导电类型的源极区域形成为与控制栅极相邻。 进入第二掺杂区域的倾斜植入物形成在选择栅极的一部分下的第一导电类型的第三掺杂区域和在控制栅极的一部分下的第一导电类型的第四掺杂区域。 漏极和源极区域与第三和第四区域相邻。

公开(公告)号：US20140295639A1

公开(公告)日：2014-10-02

申请号：US14301900

申请日：2014-06-11

申请人： FENG ZHOU ,  Frank K. Baker, JR. ,  Ko-Min Chang ,  Cheong Min Hong

发明人： FENG ZHOU ,  Frank K. Baker, JR. ,  Ko-Min Chang ,  Cheong Min Hong

IPC分类号： H01L45/00

CPC分类号： H01L45/16 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1675

摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

摘要翻译： 一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。 电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。 电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇层（911,1211） 。

公开(公告)号：US08779405B2

公开(公告)日：2014-07-15

申请号：US13486690

申请日：2012-06-01

申请人： Feng Zhou ,  Frank K. Baker, Jr. ,  Ko-Min Chang ,  Cheong Min Hong

发明人： Feng Zhou ,  Frank K. Baker, Jr. ,  Ko-Min Chang ,  Cheong Min Hong

IPC分类号： H01L29/02

CPC分类号： H01L45/16 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1675

摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

摘要翻译： 一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。 电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。 电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇（911,1211） 。

公开(公告)号：US20130320284A1

公开(公告)日：2013-12-05

申请号：US13486641

申请日：2012-06-01

申请人： Feng Zhou ,  Frank K. Baker, JR. ,  Ko-Min Chang ,  Cheong Min Hong

发明人： Feng Zhou ,  Frank K. Baker, JR. ,  Ko-Min Chang ,  Cheong Min Hong

IPC分类号： H01L45/00

CPC分类号： B82Y10/00 ,  G11C13/0007 ,  H01L45/00 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

摘要： A resistive random access memory (ReRAM) cell, comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and an interface region comprising a plurality of interspersed field focusing features that are not photo-lithographically defined. The interface region is located between the first conductive electrode and the dielectric storage material layer or between the dielectric storage material layer and the second conductive electrode.

摘要翻译： 一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。 电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。 该电池包括介于电介质存储材料层之间的第二导电电极和包含多个散布的场聚焦特征的界面区域，其不是光刻的。 界面区域位于第一导电电极和介电存储材料层之间，或位于介电存储材料层和第二导电电极之间。

公开(公告)号：US20100096686A1

公开(公告)日：2010-04-22

申请号：US12647250

申请日：2009-12-24

申请人： Chi-Nan Li ,  Cheong Min Hong

发明人： Chi-Nan Li ,  Cheong Min Hong

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/7881

摘要： An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.

摘要翻译： 电子设备可以包括包括具有第一底部和第一壁的第一沟槽的衬底。 所述电极装置还可以包括在所述第一沟槽内并且邻近所述第一壁并且覆盖所述第一沟槽的所述第一底部的第一栅极电极以及所述第一沟槽内的第一栅电极并且与所述第一栅电极相邻并且覆盖所述第一栅电极 底部的第一个沟槽。 电子设备还可以包括不连续的存储元件，其包括第一组不连续存储元件，其中第一组不连续存储元件位于（i）第一栅电极或第二栅电极之间，和（ii）第一底部的 第一沟 还描述了形成和使用电子设备的过程。