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公开(公告)号：US20240388257A1
公开(公告)日：2024-11-21
申请号：US18788533
申请日：2024-07-30
Inventor： Wen-Sheng Chen , En-Hsiang Yeh , Tzu-Jin Yeh
Abstract: A power amplifier structure includes at least one power amplifier circuit. The power amplifier circuit includes a transistor of a first type connected in series with a transistor of a second type connected between the same voltage supply. In a non-limiting nonexclusive example, an n-type transistor is connected in series with a p-type transistor connected between Vdd. The power amplifier structure can include two amplifier circuits configured in a differential amplifier structure. The differential amplifier structure includes two amplifier circuits operably connected in parallel between the same voltage supply.
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公开(公告)号：US12007436B2
公开(公告)日：2024-06-11
申请号：US18363143
申请日：2023-08-01
Inventor： Hsieh-Hung Hsieh , Yen-Jen Chen , Tzu-Jin Yeh
IPC: G01R31/28
CPC classification number: G01R31/2884 , G01R31/2853 , G01R31/2879
Abstract: An IC includes a device-under-test (DUT) configured to receive a first AC signal at a first node and output a second AC signal at a second node, the second AC signal being based on the first AC signal, and first and second detection circuits. Each of the first and second detection circuits includes a first gain stage coupled to a corresponding one of the first or second nodes through a first capacitive device, a second gain stage in a cascade arrangement with the first gain stage, and a low-pass filter configured to generate a DC signal based on an output signal of the second gain stage.
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公开(公告)号：US11906598B2
公开(公告)日：2024-02-20
申请号：US17818141
申请日：2022-08-08
Inventor： Hsieh-Hung Hsieh , Wu-Chen Lin , Yen-Jen Chen , Tzu-Jin Yeh
CPC classification number: G01R31/40 , G01R29/0871 , H03F3/211 , H03F3/245 , H03F2200/267 , H03F2200/451
Abstract: A testing system includes: a dividing circuit configured to receive a testing signal and provide a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit, each of the plurality of power-amplifier chips being configured to be tested by receiving a respective input signal of the plurality of input signals and generating a respective output signal for a predetermined testing time.
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公开(公告)号：US11817385B2
公开(公告)日：2023-11-14
申请号：US17389795
申请日：2021-07-30
Inventor： Chiao-Han Lee , Chi-Hsien Lin , Ho-Hsiang Chen , Hsien-Yuan Liao , Tzu-Jin Yeh , Ying-Ta Lu
IPC: H01L23/522 , H01L23/58 , H01L23/64 , H01L49/02 , H01L23/528 , H01L23/00
CPC classification number: H01L23/5227 , H01L23/528 , H01L23/5286 , H01L23/562 , H01L23/585 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit includes an inductor that includes a first set of conductive lines in a first metal layer, and is over a substrate, and a guard ring. The guard ring includes a first conductive line in a second metal layer, and extending in a first direction, a second conductive line extending in a second direction, and a first staggered line coupled between the first conductive line and the second conductive line. The first staggered line includes a second set of conductive lines in the second metal layer, and extends in the first direction, a third set of conductive lines in a third metal layer, and extends in the second direction, and a first set of vias coupling the second and third set of conductive lines together. All metal lines in the third metal layer that are part of the guard ring extend in the second direction.
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公开(公告)号：US11736064B2
公开(公告)日：2023-08-22
申请号：US17732400
申请日：2022-04-28
Inventor： Chi-Hsien Lin , Ho-Hsiang Chen , Hsien-Yuan Liao , Tzu-Jin Yeh , Ying-Ta Lu
CPC classification number: H03B5/1228 , H03B1/04 , H03B5/1203 , H03B5/1206 , H03B5/1212 , H03B5/1243 , H03B5/1296 , H03H7/0161 , H03B2200/009
Abstract: A differential oscillator includes a differential circuit and a transformer-coupled band-pass filter (BPF) coupled between first and second output nodes. The BPF includes a coupling device coupled between the output nodes and a transformer including first and second windings in a metal layer of an IC. The first winding includes first and second conductive structures coupled to the first output node and a voltage node, respectively, and a third conductive structure including first and second extending portions connected to the first and second conductive structures, respectively. The second winding includes a fourth conductive structure including a third extending portion coupled to the voltage node and a fourth extending portion coupled to the second output node. The third extending portion is between the second conductive structure and the first extending portion, and the fourth extending portion is between the first conductive structure and the second extending portion.
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Patent Agency Ranking
公开(公告)号：US20230125874A1
公开(公告)日：2023-04-27
申请号：US17695500
申请日：2022-03-15
Inventor： Wen-Sheng Chen , En-Hsiang Yeh , Tzu-Jin Yeh
Abstract: A power amplifier structure includes at least one power amplifier circuit. The power amplifier circuit includes a transistor of a first type connected in series with a transistor of a second type connected between the same voltage supply. In a non-limiting nonexclusive example, an n-type transistor is connected in series with a p-type transistor connected between Vdd. The power amplifier structure can include two amplifier circuits configured in a differential amplifier structure. The differential amplifier structure includes two amplifier circuits operably connected in parallel between the same voltage supply.
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公开(公告)号：US10453809B2
公开(公告)日：2019-10-22
申请号：US15495077
申请日：2017-04-24
Inventor： Chia-Chung Chen , Chi-Feng Huang , Shu Fang Fu , Tzu-Jin Yeh , Chewn-Pu Jou
IPC: H01L21/762 , H01L29/417 , H01L29/78 , H01L21/761 , H01L23/66 , H01L29/66 , H01L29/10 , H01L21/265 , H01L27/06 , H01L49/02 , H01L29/06 , H01L29/45
Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.
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公开(公告)号：US20170229406A1
公开(公告)日：2017-08-10
申请号：US15495077
申请日：2017-04-24
Inventor： Chia-Chung Chen , Chi-Feng Huang , Shu Fang Fu , Tzu-Jin Yeh , Chewn-Pu Jou
Abstract: A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.
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公开(公告)号：US09255963B2
公开(公告)日：2016-02-09
申请号：US14252886
申请日：2014-04-15
Inventor： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
CPC classification number: G01R31/2824 , H03L5/00
Abstract: A device comprises a radio frequency peak detector configured to receive an ac signal from a voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector and a feedback control unit coupled between an output of the radio frequency peak detector and an input of the voltage controlled oscillator.
Abstract translation: 一种设备包括：射频峰值检测器，被配置为从压控振荡器接收交流信号，并在射频峰值检测器的输出处产生与ac信号成比例的直流值，以及反馈控制单元，其耦合在无线电 频率峰值检测器和压控振荡器的输入。
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公开(公告)号：US20240363461A1
公开(公告)日：2024-10-31
申请号：US18309277
申请日：2023-04-28
Inventor： Hsieh-Hung Hsieh , Chen Cheng Chou , Hwa-Yu Yang , Ming-Da Cheng , Ru-Shang Hsiao , Tzu-Jin Yeh , Ching-Hui Chen , Shenggao Li
IPC: H01L23/31 , H01L23/00 , H01L23/498 , H01L23/66 , H01L27/02
CPC classification number: H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/66 , H01L24/32 , H01L27/0207 , H01L2223/6616 , H01L2223/6655 , H01L2224/16225 , H01L2924/14215
Abstract: A device including a substrate, a front-end module circuit situated over the substrate and configured to provide radio frequency communications, and a wafer-level chip-scale package circuit situated over the front-end module circuit and connected to the front-end module circuit and configured to provide passive components for radio frequency communications.
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