公开(公告)号：US11812646B2

公开(公告)日：2023-11-07

申请号：US17580659

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Yu Wu ,  Mirng-Ji Lii ,  Shang-Yun Tu ,  Ching-Hui Chen

IPC: H01L21/00 ,  H10K59/131 ,  H10K59/121 ,  H10K71/00

CPC classification number: H10K59/131 ,  H10K59/121 ,  H10K71/00

Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

公开(公告)号：US20220149141A1

公开(公告)日：2022-05-12

申请号：US17580659

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Yu Wu ,  Mirng-Ji Lii ,  Shang-Yun Tu ,  Ching-Hui Chen

IPC: H01L27/32 ,  H01L51/56

Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

公开(公告)号：US20200176254A1

公开(公告)日：2020-06-04

申请号：US16694121

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Kang Chin Wei ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/3213

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20180226342A1

公开(公告)日：2018-08-09

申请号：US15942762

申请日：2018-04-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L21/48 ,  H01L23/532

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

公开(公告)号：US11502402B2

公开(公告)日：2022-11-15

申请号：US16738420

申请日：2020-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Feng Wei Kuo ,  Wen-Shiang Liao ,  Ching-Hui Chen

IPC: H01L23/66 ,  H01Q1/48 ,  H01Q9/04 ,  H01L21/56

Abstract: A device includes a ground plane electrically connected to a proximal end of at least one conductive pillar and an antenna pad substantially parallel to the ground plane, wherein the antenna pad is separated from a distal end of the at least one conductive pillar by a dielectric pad having a first dielectric constant, wherein the ground plane, the at least one conductive pillar, and the dielectric pad surround an antenna cavity filled with a dielectric fill material having a second dielectric constant different from the first dielectric constant.

公开(公告)号：US09935047B2

公开(公告)日：2018-04-03

申请号：US14885719

申请日：2015-10-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kio-Chio Liu

IPC: H01L23/522 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L21/76808 ,  H01L21/76877 ,  H01L23/3192 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2924/014

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

公开(公告)号：US20240363461A1

公开(公告)日：2024-10-31

申请号：US18309277

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsieh-Hung Hsieh ,  Chen Cheng Chou ,  Hwa-Yu Yang ,  Ming-Da Cheng ,  Ru-Shang Hsiao ,  Tzu-Jin Yeh ,  Ching-Hui Chen ,  Shenggao Li

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01L27/02

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/66 ,  H01L24/32 ,  H01L27/0207 ,  H01L2223/6616 ,  H01L2223/6655 ,  H01L2224/16225 ,  H01L2924/14215

Abstract: A device including a substrate, a front-end module circuit situated over the substrate and configured to provide radio frequency communications, and a wafer-level chip-scale package circuit situated over the front-end module circuit and connected to the front-end module circuit and configured to provide passive components for radio frequency communications.

公开(公告)号：US11004685B2

公开(公告)日：2021-05-11

申请号：US16694121

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/8238 ,  H01L27/092

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US10700001B2

公开(公告)日：2020-06-30

申请号：US15942762

申请日：2018-04-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

公开(公告)号：US20170110401A1

公开(公告)日：2017-04-20

申请号：US14885719

申请日：2015-10-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kio-Chio Liu

IPC: H01L23/522 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L21/76808 ,  H01L21/76877 ,  H01L23/3192 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2924/014

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.