公开(公告)号：US20210149632A1

公开(公告)日：2021-05-20

申请号：US17156731

申请日：2021-01-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Puneet Sabbarwal ,  Pankaj Gupta

IPC: G06F7/24 ,  G06F5/06

Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

公开(公告)号：US10484224B2

公开(公告)日：2019-11-19

申请号：US15942614

申请日：2018-04-02

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi ,  Pankaj Gupta ,  Indu Prathapan

IPC: H04L27/26

Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

公开(公告)号：US20190317855A1

公开(公告)日：2019-10-17

申请号：US16453081

申请日：2019-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Prashanth Saraf ,  Desmond Pravin Martin Fernandes ,  Saket Jalan

IPC: G06F11/10 ,  G06F3/06 ,  G11C11/56 ,  G11C11/16 ,  G11C5/04 ,  H03M13/37 ,  H03M13/35 ,  H03M13/19 ,  G11C7/22 ,  G11C7/10

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

公开(公告)号：US10330773B2

公开(公告)日：2019-06-25

申请号：US15184715

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Sandeep Rao ,  Karthik Ramasubramanian ,  Indu Prathapan ,  Raghu Ganesan ,  Pankaj Gupta

IPC: G01S7/02 ,  G01S13/34 ,  H04B15/02 ,  H04L27/10 ,  G01S7/35

Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

公开(公告)号：US20180107541A1

公开(公告)日：2018-04-19

申请号：US15844259

申请日：2017-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abishek Ganapati Karkisaval

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US12045582B2

公开(公告)日：2024-07-23

申请号：US17351699

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Karthik Subburaj ,  Sujaata Ramalingam ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G06F7/49 ,  G06F7/501 ,  G06F17/14

CPC classification number: G06F7/49 ,  G06F7/501 ,  G06F17/142

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

公开(公告)号：US12021552B2

公开(公告)日：2024-06-25

申请号：US17566047

申请日：2021-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik Subburaj ,  Pranav Sinha ,  Mayank Kumar Singh ,  Rittu Sachdev ,  Karan Singh Bhatia ,  Shailesh Joshi ,  Indu Prathapan

IPC: H04B1/00 ,  H04B1/04 ,  H04B1/10 ,  H04B1/69

CPC classification number: H04B1/0075 ,  H04B1/04 ,  H04B1/1036 ,  H04B1/69 ,  H04B2001/0408 ,  H04B2001/1045 ,  H04B2001/1063 ,  H04B2001/6912

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

公开(公告)号：US11927689B2

公开(公告)日：2024-03-12

申请号：US17351750

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata Ramalingam ,  Karthik Subburaj ,  Pankaj Gupta ,  Anil Varghese Mani ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G01S7/292 ,  G01S7/40 ,  G01S13/524

CPC classification number: G01S7/2922 ,  G01S7/4004 ,  G01S13/5246

Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.

公开(公告)号：US20230418555A1

公开(公告)日：2023-12-28

申请号：US18335452

申请日：2023-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Puneet Sabbarwal ,  Pankaj Gupta

IPC: G06F7/24 ,  G06F5/06

CPC classification number: G06F7/24 ,  G06F5/065 ,  G06F2207/228

Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

公开(公告)号：US11740968B2

公开(公告)日：2023-08-29

申请号：US17824605

申请日：2022-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1012 ,  G06F11/1048 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.