中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

41 records (took 0.019 seconds)

    INPUT PATH MATCHING IN PIPELINED CONTINUOUS-TIME ANALOG-TO-DIGITAL CONVERTERS
    21.
    发明申请
    INPUT PATH MATCHING IN PIPELINED CONTINUOUS-TIME ANALOG-TO-DIGITAL CONVERTERS 审中-公开

    公开(公告)号：US20190222223A1

    公开(公告)日：2019-07-18

    申请号：US16141671

    申请日：2018-09-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Venkatesh Srinivasan ,  Kun Shi ,  Victoria Wang ,  Nikolaus Klemmer

    IPC: H03M3/00 ,  H03K5/159 ,  H03M1/00

    CPC classification number: H03M3/38 ,  H03K5/159 ,  H03M1/001 ,  H03M1/164 ,  H03M3/37 ,  H03M3/386 ,  H03M3/464

    Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

    PLL lock range extension over temperature
    23.
    发明授权
    PLL lock range extension over temperature 有权

    公开(公告)号：US10187071B2

    公开(公告)日：2019-01-22

    申请号：US15387636

    申请日：2016-12-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Himanshu Arora ,  Siraj Akhtar ,  Lu Sun ,  Hamid Safiri ,  Wenjing Lu ,  Nikolaus Klemmer

    IPC: H03L7/099 ,  H03L7/10 ,  H03L1/02

    Abstract: A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.

    OSCILLATOR WITH PULSE-EDGE TUNING
    26.
    发明申请
    OSCILLATOR WITH PULSE-EDGE TUNING 审中-公开

    公开(公告)号：US20170207747A1

    公开(公告)日：2017-07-20

    申请号：US15408399

    申请日：2017-01-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Petteri Matti Litmanen ,  Nikolaus Klemmer

    IPC: H03B5/24 ,  H04L27/00

    Abstract: An oscillator architecture with pulse-edge tuning. The oscillator includes a signal generator generating at least two signal frequencies, and a logic circuit (such as an AND gate) that combines the signal frequencies to generate a corresponding oscillator signal. The logic circuit includes a pull-up PMOS transistor coupled to a high rail, and a pull-down NMOS transistor coupled to a low rail. Duty cycle tuning/correction circuitry includes high and low side tuning FETs: a high-side tuning PMOS transistor is coupled between the high rail and a source terminal of the pull-up PMOS transistor, and a low-side tuning NMOS transistor is coupled between the low rail and a source terminal of the pull-down NMOS transistor. Both tuning FETs are controlled for operation as a variable resistor by respective high-side and low-side DACs (digital to analog converters) configure to provide a tuning control signals to the tuning FETs (variable resistance) based on respective input digital tuning/correction signals. In an example application, the oscillator design is adapted for a direct conversion RF transmit chain including an I-Path and a Q-Path: the signal generator generates ±I and ±Q differential signal frequencies, and each signal frequency is generated by a separate logic circuit (such as an AND gate), including pulse-edge tuning/correction circuitry.

    Input Path Matching in Pipelined Continuous-Time Analog-to-Digital Converters
    27.
    发明申请
    Input Path Matching in Pipelined Continuous-Time Analog-to-Digital Converters 有权
    流水线连续模拟数字转换器中的输入路径匹配

    公开(公告)号：US20160269045A1

    公开(公告)日：2016-09-15

    申请号：US15068231

    申请日：2016-03-11

    Applicant: Texas Instruments Incorporated

    Inventor： Venkatesh Srinivasan ,  Kun Shi ,  Victoria Wang ,  Nikolaus Klemmer

    IPC: H03M3/00 ,  H03K5/159

    CPC classification number: H03M3/38 ,  H03K5/159 ,  H03M1/001 ,  H03M1/164 ,  H03M3/37 ,  H03M3/386 ,  H03M3/464

    Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

    Abstract translation: 在流水线连续时间模数转换器（ADC）中的输入路径匹配的系统和方法，包括基于流水线连续时间三角调制器（CTDSM）的ADC，包括设置在连续时间输入路径中的输入延迟电路， 将模拟输入信号输入到连续时间ADC的第一求和电路。 至少一个数字延迟线设置在耦合到第一求和电路的较低级子ADC（多个流水线式子ADC）的输出与子数字 - 模拟转换器（DAC）之间， 并且在较低级的副ADC与数字噪声消除滤波器之间。 数字延迟线被配置为使得能够根据输入延迟匹配电路的过程变化来校准提供给子DAC和数字噪声消除滤波器的前级子ADC的输出延迟，以最小化残留输出 在第一个求和电路。

    MASTER-SLAVE SYSTEM WITH TRIGGERED REMOTE FUNCTION CALLS
    28.
    发明申请
    MASTER-SLAVE SYSTEM WITH TRIGGERED REMOTE FUNCTION CALLS 审中-公开
    具有触发远程功能调用的主从系统

    公开(公告)号：US20160048470A1

    公开(公告)日：2016-02-18

    申请号：US14822175

    申请日：2015-08-10

    Applicant: Texas Instruments Incorporated

    Inventor： Xiaoxi Zhang ,  Nikolaus Klemmer ,  Hunsoo Choo

    IPC: G06F13/364 ,  G06F13/24 ,  G06F13/42

    CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/4282

    Abstract: Triggered remote function calls can be used in master-slave systems to trigger slave-side software functions pre-loaded by a master into slave MCU memory, with associated parameters pre-loaded into a slave function interface memory. A master issues trigger-function signals (such as rising/falling edges or signal levels) over a trigger-function signal line. The slave includes a trigger conditioning block that in response issues a trigger-function request to the slave MCU, which calls/executes the associated software function, including accessing the associated trigger-function parameters from function interface memory. A slave can include a hardware function block with functionality configurable by a pre-loaded software configuration function (with associated parameters). A master can include a hardware function block configured to issue trigger-function signals. The slave (trigger conditioning block) can be configured to service trigger-function signals as an IRQ (interrupt request) to the MCU, which executes an ISR (interrupt service routine) as a triggered function call.

    Abstract translation: 触发的远程功能调用可以在主从系统中使用，以将主机预加载的从机软件功能触发到从MCU存储器中，并将相关参数预加载到从功能接口存储器中。 主机通过触发功能信号线发出触发功能信号（如上升沿/下降沿或信号电平）。 从设备包括一个触发调节块，它响应发出一个触发功能请求给从MCU，从机MCU调用/执行相关的软件功能，包括从功能接口存储器访问相关的触发功能参数。 从机可以包括硬件功能块，其功能可通过预加载的软件配置功能（具有相关参数）配置。 主机可以包括配置为发出触发功能信号的硬件功能块。 从机（触发条件块）可以被配置为将触发功能信号作为IRQ（中断请求）提供给MCU，该MCU执行ISR（中断服务程序）作为触发的函数调用。

    Method and Apparatus Having Enhanced Oscillator Phase Noise Using High Vt MOS Devices
    29.
    发明申请
    Method and Apparatus Having Enhanced Oscillator Phase Noise Using High Vt MOS Devices 有权
    使用高Vt MOS器件增强振荡器相位噪声的方法和装置

    公开(公告)号：US20150333698A1

    公开(公告)日：2015-11-19

    申请号：US14712336

    申请日：2015-05-14

    Applicant: Texas Instruments Incorporated

    Inventor： Himanshu Arora ,  Siraj Akhtar ,  Nikolaus Klemmer

    IPC: H03B5/12 ,  G06F17/50 ,  H03K3/013

    CPC classification number: G06F17/50 ,  G06F17/505 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B2200/009 ,  H03K3/013

    Abstract: A voltage-controlled oscillator (VCO), includes a resonator circuit connected to receive an input voltage and having a first output node and a second output node; and at least one cross-coupled switching circuit portion, each cross-coupled switching circuit portion comprising a first transistor having a drain connected to the first output node and a second transistor having a drain connected to the second output node, the first transistor having a gate connected between the drain of the second transistor and the second output node and the second transistor having a gate connected between the drain of the first transistor and the first output node, each of the first and second transistors having a threshold voltage that is determined to be the highest threshold voltage available for the process used to create the VCO.

    Abstract translation: 压控振荡器（VCO）包括连接以接收输入电压并具有第一输出节点和第二输出节点的谐振器电路; 和至少一个交叉耦合开关电路部分，每个交叉耦合的开关电路部分包括具有连接到第一输出节点的漏极的第一晶体管和连接到第二输出节点的漏极的第二晶体管，第一晶体管具有 连接在第二晶体管的漏极和第二输出节点之间的栅极，第二晶体管具有连接在第一晶体管的漏极和第一输出节点之间的栅极，第一和第二晶体管中的每一个具有阈值电压，其被确定为 是可用于创建VCO的过程的最高阈值电压。

    Bit slicer circuit for S-FSK receiver, integrated circuit, and method associated therewith
    30.
    发明授权
    Bit slicer circuit for S-FSK receiver, integrated circuit, and method associated therewith 有权

    公开(公告)号：US11265191B2

    公开(公告)日：2022-03-01

    申请号：US16944562

    申请日：2020-07-31

    Applicant: Texas Instruments Incorporated

    Inventor： Nikolaus Klemmer ,  Amneh Mohammed Akour ,  Abhijit Anant Patki ,  Timothy Patrick Pauletti ,  Tarkesh Pande

    IPC: H04L27/14 ,  H04L27/06 ,  H04B1/69

    Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

Patent Agency Ranking