公开(公告)号：US20250126883A1

公开(公告)日：2025-04-17

申请号：US18991919

申请日：2024-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H10D84/83 ,  H01L21/02 ,  H01L21/283 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H10D30/60 ,  H10D62/00 ,  H10D62/10 ,  H10D62/13 ,  H10D64/01 ,  H10D64/27 ,  H10D64/66 ,  H10D84/01 ,  H10D84/03

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US11815804B2

公开(公告)日：2023-11-14

申请号：US17481673

申请日：2021-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Hsun Lin ,  Pei-Cheng Hsu ,  Ching-Fang Yu ,  Ta-Cheng Lien ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC: G03F1/24

CPC classification number: G03F1/24

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.

公开(公告)号：US11143954B2

公开(公告)日：2021-10-12

申请号：US16018444

申请日：2018-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chang Hsueh ,  Ta-Cheng Lien ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC: G03F1/70 ,  G03F1/38 ,  G03F1/54 ,  G03F1/24 ,  G03F1/36

Abstract: Photomasks and methods of fabricating the photomasks are provided herein. In some examples, a layout for forming an integrated circuit device is received. The layout includes a set of printing features. A region of the layout is identified. The region is at a distance from the set of printing features such that an exposure region associated with a feature in the region does not affect a set of exposure regions associated with the set of printing features. A plurality of non-printing features is inserted into the region. A photomask is fabricated based on the layout.

公开(公告)号：US20190391480A1

公开(公告)日：2019-12-26

申请号：US16018444

申请日：2018-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chang Hsueh ,  Ta-Cheng Lien ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC: G03F1/20 ,  G03F1/38 ,  G03F1/78 ,  G03F1/24 ,  G03F1/54 ,  G03F7/20 ,  H01L21/033

Abstract: Photomasks and methods of fabricating the photomasks are provided herein. In some examples, a layout for forming an integrated circuit device is received. The layout includes a set of printing features. A region of the layout is identified. The region is at a distance from the set of printing features such that an exposure region associated with a feature in the region does not affect a set of exposure regions associated with the set of printing features. A plurality of non-printing features is inserted into the region. A photomask is fabricated based on the layout.

公开(公告)号：US20190196322A1

公开(公告)日：2019-06-27

申请号：US15851829

申请日：2017-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Chien-Cheng Chen ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Pei-Cheng Hsu ,  Yih-Chen Su ,  Gaston Lee ,  Tran-Hui Shen

IPC: G03F1/24 ,  G03F1/54 ,  G03F7/20

CPC classification number: G03F1/24 ,  G03F1/54 ,  G03F7/2004

Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.

公开(公告)号：US20180149959A1

公开(公告)日：2018-05-31

申请号：US15670183

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Anthony Yen ,  Chin-Hsiang Lin

IPC: G03F1/24 ,  G03F1/54 ,  G03F1/42 ,  G03F1/26 ,  G03F1/48

CPC classification number: G03F1/24 ,  G03F1/26 ,  G03F1/42 ,  G03F1/48 ,  G03F1/50 ,  G03F1/54

Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.

公开(公告)号：US12218130B2

公开(公告)日：2025-02-04

申请号：US18526290

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US20220359510A1

公开(公告)日：2022-11-10

申请号：US17872417

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US11349014B2

公开(公告)日：2022-05-31

申请号：US16917577

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US11327405B2

公开(公告)日：2022-05-10

申请号：US17080652

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Cheng Chen ,  Chia-Jen Chen ,  Hsin-Chang Lee ,  Shih-Ming Chang ,  Tran-Hui Shen ,  Yen-Cheng Ho ,  Chen-Shao Hsu

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/78 ,  H01J37/317 ,  G03F1/76

Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.