公开(公告)号：US20200058508A1

公开(公告)日：2020-02-20

申请号：US16210641

申请日：2018-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni YU ,  Zhi-Chang LIN ,  Wei-Hao WU ,  Huan-Chieh SU ,  Chung-Wei HSU ,  Chih-Hao WANG

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66

Abstract: A method for forming a FinFET device structure is provided. The method for foiming a FinFET device structure includes forming a fin structure and a fin isolation structure over a substrate, and forming a metal stack over the fin structure and the fin isolation structure. The method for forming a FinFET device structure also includes partially removing the metal stack so that a top surface of the fin isolation structure is exposed, and forming a dielectric material over the metal stack and covering the top surface of the fin isolation structure. The method for forming a FinFET device structure further includes patterning the dielectric material and the metal stack to form a metal gate structure and an insulating structure over the metal gate structure.

公开(公告)号：US20190088762A1

公开(公告)日：2019-03-21

申请号：US15706456

申请日：2017-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh SU ,  Zhi-Chang LIN ,  Ting-Hung HSU ,  Jia-Ni YU ,  Wei-Hao WU ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes forming a gate electrode layer in a gate trench; filling a recess in the gate electrode layer with a dielectric feature; and etching back the gate electrode layer from top end surfaces of the gate electrode layer while leaving a portion of the gate electrode layer under the dielectric feature.

公开(公告)号：US20180174919A1

公开(公告)日：2018-06-21

申请号：US15476068

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh SU ,  Chih-Hao WANG ,  Jui-Chen HUANG ,  Chun-Hsiung LIN

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/823814 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02639 ,  H01L21/0273 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method of forming a semiconductor device includes forming first and second fin structures on a substrate and a patterned polysilicon structure on first portions of the first and second fin structures. The method further includes depositing an insulating layer on second portions of the first and second fin structures and on the patterned polysilicon structure, which may be followed by selectively removing the insulating layer from the second portions and patterning a first hard mask layer on the second portion of the second fin structure. The method also includes growing a first epitaxial region on the second portion of the first fin structure, removing the patterned first hard mask layer from the second portion of the second fin structure, patterning a second hard mask layer on the first epitaxial region, and growing a second epitaxial region on the second portion of the second fin structure.

公开(公告)号：US20240429292A1

公开(公告)日：2024-12-26

申请号：US18489367

申请日：2023-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Huan-Chieh SU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

Abstract: The present disclosure describes a semiconductor device having a contact structure isolated from a source/drain structure. The semiconductor structure includes a gate structure on a substrate, first and second source/drain (S/D) structures on opposite sides of the gate structure, an isolation layer on the second S/D structure, a third S/D structure adjacent to and separate from the second S/D structure, and a S/D contact structure on the isolation layer and the third S/D structure. The isolation layer separates the S/D contact structure from the second S/D structure.

公开(公告)号：US20240371971A1

公开(公告)日：2024-11-07

申请号：US18487920

申请日：2023-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Lo-Heng CHANG ,  Huan-Chieh SU ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit includes a transistor having a plurality of stacked channels. The transistor includes a source/drain region in contact with the channel regions. The transistor includes a silicide in contact with the top of the source/drain region and extending vertically along a sidewall of the silicide. A source/drain contact is in contact with a top of the silicide and extending vertically along a sidewall of the silicide.

公开(公告)号：US20240258158A1

公开(公告)日：2024-08-01

申请号：US18630814

申请日：2024-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Huan-Chieh SU ,  Lin-Yu HUANG ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/7682 ,  H01L21/0259 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.

公开(公告)号：US20230268403A1

公开(公告)日：2023-08-24

申请号：US17858861

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi CHUANG ,  Li-Zhen YU ,  Huan-Chieh SU ,  Chun-Yuan CHEN ,  Lin-Yu HUANG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/66439

Abstract: A device includes semiconductor device structure includes a first dielectric layer. A first plurality of nanostructures are disposed on the first dielectric layer, with the first plurality of nanostructures overlying one another. A first source/drain region is disposed laterally adjacent to a first side of the first plurality of nanostructures. A second dielectric layer is on a first side of the first source/drain region. A front side source/drain contact is disposed on a second side of the first source/drain region that is opposite the first side, and a backside source/drain contact is disposed on the first side of the first source/drain region. The backside source/drain contact extends through the second dielectric layer.

公开(公告)号：US20230138012A1

公开(公告)日：2023-05-04

申请号：US17743352

申请日：2022-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Huan-Chieh SU ,  Li-Zhen YU ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

公开(公告)号：US20220406909A1

公开(公告)日：2022-12-22

申请号：US17720276

申请日：2022-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan CHIU ,  Lo-Heng CHANG ,  Huan-Chieh SU ,  Cheng-Chi CHUANG ,  Yun Ju FAN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/265 ,  H01L21/266 ,  H01L21/285 ,  H01L29/66

Abstract: A device includes a substrate, a gate structure, a source/drain region, a first silicide layer, a second silicide layer and a contact. The gate structure wraps around at least one vertical stack of nanostructure channels. The source/drain region abuts the gate structure. The first silicide layer includes a first metal component on the source/drain region. The second silicide layer includes a second metal component different than the first metal component, and is on the first silicide layer. The contact is on the second silicide layer.

公开(公告)号：US20220359685A1

公开(公告)日：2022-11-10

申请号：US17814098

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen YU ,  Cheng-Chi CHUANG ,  Chih-Hao WANG ,  Huan-Chieh SU ,  Lin-Yu HUANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78

Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.