中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

260 records (took 0.028 seconds)

    Gate structures for stacked semiconductor devices
    21.
    发明授权
    Gate structures for stacked semiconductor devices 有权

    公开(公告)号：US11776960B2

    公开(公告)日：2023-10-03

    申请号：US17461329

    申请日：2021-08-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mrunal Abhijith Khaderbad ,  Sathaiya Mahaveer Dhanyakumar ,  Huicheng Chang ,  Keng-Chu Lin

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L27/0924 ,  H01L21/823821

    Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    27.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE 有权

    公开(公告)号：US20230042196A1

    公开(公告)日：2023-02-09

    申请号：US17670740

    申请日：2022-02-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Chang Lin ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

    IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234

    Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    28.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20230038762A1

    公开(公告)日：2023-02-09

    申请号：US17650112

    申请日：2022-02-07

    Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

    Inventor： Szu-Ying Chen ,  Po-Kang Ho ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762

    Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.

    METHOD FOR ION IMPLANTATION UNIFORMITY CONTROL
    29.
    发明申请
    METHOD FOR ION IMPLANTATION UNIFORMITY CONTROL 有权

    公开(公告)号：US20230016619A1

    公开(公告)日：2023-01-19

    申请号：US17684876

    申请日：2022-03-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tien-Shun Chang ,  Yu-Kang Liu ,  Su-Hao Liu ,  Huicheng Chang ,  Yee-Chia Yeo

    IPC: H01J37/317 ,  H01J37/304

    Abstract: A method includes moving a plurality of sensors along a translation path with respect to an ion beam, acquiring sensor signals produced by the plurality of sensors, converting the acquired sensor signals into a data set representative of a two-dimensional (2D) profile of the ion beam, generating a plurality of first one-dimensional (1D) profiles of the ion beam from the data set, generating a plurality of second 1D profiles of the ion beam by spatially inverting each of the plurality of first 1D profiles, generating a plurality of third 1D profiles of the ion beam by superposing first current density values of each of the plurality of first 1D profiles with second current density values of a corresponding one of the plurality of second 1D profiles and determining whether to continue an implantation process with the ion beam in accordance with the plurality of third 1D profiles.

Patent Agency Ranking