公开(公告)号：US10211307B2

公开(公告)日：2019-02-19

申请号：US15653068

申请日：2017-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/04 ,  H01L29/165

Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.

公开(公告)号：US10163731B2

公开(公告)日：2018-12-25

申请号：US15485428

申请日：2017-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/84 ,  H01L29/04 ,  H01L27/13 ,  H01L23/00 ,  H01L27/12 ,  H01L21/762 ,  H01L21/8238

Abstract: A FinFET semiconductor structure includes first fins and second fins extended from a semiconductor substrate, and a gate structure disposed over the first fins and the second fins. Each first fin includes a first semiconductor portion connected to the semiconductor substrate and a second semiconductor portion over the semiconductor substrate. Each second fin includes the first semiconductor portion connected to the semiconductor substrate, the second semiconductor portion, and at least one spacer at least partially disposed between the first semiconductor portion and the second semiconductor portion. The semiconductor substrate and the first semiconductor portion respectively have a surface oriented on a first crystal plane, the second semiconductor portion has a surface oriented on a second crystal plane, wherein the first crystal plane is oriented differently than the second crystal plane.

公开(公告)号：US20180269109A1

公开(公告)日：2018-09-20

申请号：US15987009

申请日：2018-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02247 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02634 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.

公开(公告)号：US10008414B2

公开(公告)日：2018-06-26

申请号：US15261302

申请日：2016-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02247 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02634 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

Abstract: A FinFET includes a semiconductor layer having a fin structure that protrudes out of the semiconductor layer. The fin structure includes a first segment and a second segment disposed over the first segment. A dielectric layer is disposed over the semiconductor layer. The first segment of the fin structure is surrounded by the dielectric layer. A metal layer is disposed over the dielectric layer. The second segment of the fin structure is surrounded by the metal layer. The dielectric layer has a greater nitrogen content than the metal layer. The first segment of the fin structure also has a first side surface that is rougher than a second side surface of the second segment of the fin structure.

公开(公告)号：US20180175029A1

公开(公告)日：2018-06-21

申请号：US15379632

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Ying-Keung Leung ,  Chi On Chui

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/785

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.

公开(公告)号：US12218136B2

公开(公告)日：2025-02-04

申请号：US17861565

申请日：2022-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, source/drain structures, and a contact structure. The semiconductor fin extends from a substrate. The gate structure extends across the semiconductor fin. The source/drain structures are on opposite sides of the gate structure. The contact structure is over a first one of the source/drain structures. The contact structure includes a semiconductor contact and a metal contact over the semiconductor contact. The semiconductor contact has a higher dopant concentration than the first one of the source/drain structures. The first one of the source/drain structures includes a first portion and a second portion at opposite sides of the fin and interfacing the semiconductor contact.

公开(公告)号：US12027625B2

公开(公告)日：2024-07-02

申请号：US18070285

申请日：2022-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao Kuo ,  Jung-Hao Chang ,  Chao-Hsien Huang ,  Li-Te Lin ,  Kuo-Cheng Ching

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/02532 ,  H01L21/0262 ,  H01L2029/7858

Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

公开(公告)号：US20230378330A1

公开(公告)日：2023-11-23

申请号：US18358276

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning JU ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/6681 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/785 ,  H01L21/3086

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

公开(公告)号：US11764286B2

公开(公告)日：2023-09-19

申请号：US17379208

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/6656 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.

公开(公告)号：US11522074B2

公开(公告)日：2022-12-06

申请号：US17200226

申请日：2021-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Keng-Chu Lin ,  Shi-Ning Ju

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, a gate structure, a plurality of source/drain structures, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin extends upwardly from the substrate. The second semiconductor fin extends upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The source/drain structures are on the first and second semiconductor fins. The STI oxide extends continuously between the first and second semiconductor fins and has a U-shaped profile when viewed in a cross section taken along a lengthwise direction of the gate structure. The dielectric layer is partially embedded in the STI oxide and has a U-shaped profile when viewed in the cross section taken along the lengthwise direction of the gate structure.